Delay time sensitivity in nonlinear monotone RC trees. - Navneet K. Jain; V. C. Prasad; A. B. Bhattacharyya (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

CPM Pole-Zero Computation Using The Generalized Eigenproblem Approach. - Ram Singh Rana; A. B. Bhattacharyya (VLSI Design, 1992)

LATCHSIM - A Lath-Up Simulator in VLSI CAD Environment for CMOS and BiCMOS Circuits. - A. Bandyopadhyay; P. R. Verma; A. B. Bhattacharyya; M. J. Zarabi (VLSI Design, 1994)

A micropower analog hearing aid on low voltage CMOS digital process. - A. B. Bhattacharyya; Ram Singh Rana; S. K. Guha; Rajendar Bahl; Sneh Anand; M. J. Zarabi; P. A. Govindacharyulu; Vivek Gupta; Vivek Mohan; Jatin Roy; Amul Atri (VLSI Design, 1996)

Sub-Circuit Analysis for Power Supply Rejection Ratio in Regulated Cascode Operational Transconductance Amplifiers and Filters. - A. B. Bhattacharyya; Saudas Dey (VLSI Design, 1999)

PREDICTMOS MOSFET Model and its Application to Submicron CMOS Inverter Delay Analysis. - A. B. Bhattacharyya; Shrutin Ulman (ASP-DAC/VLSI Design, 2002)

Compact MOSFET Models for Low Power Analog CMOS Design. - A. B. Bhattacharyya (VLSI Design, 2005)

Extended-Sakurai-Newton MOSFET Model for Ultra-Deep-Submicrometer CMOS Digital Design. - Nishant Chandra; Apoorva Kumar Yati; A. B. Bhattacharyya (VLSI Design, 2009)

Analysis of Second-Order Effect Components of Drain Conductance and Its Implication on Output Resistance of Wilson Current Mirror. - Kirmender Singh; A. B. Bhattacharyya (VLSID, 2015)