A "Design for Verification" Methodology. - F. Sforza; L. Battú; M. Brunelli; A. Castelnuovo; M. Magnaghi (ISQED, 2001)

Emulation-Based Design Errors Identification. - A. Castelnuovo; Alessandro Fin; Franco Fummi; F. Sforza (DFT, 2002)

A 1000X speed up for properties completeness evaluation. - A. Castelnuovo; Andrea Fedeli; Alessandro Fin; Franco Fummi; Graziano Pravadelli; Umberto Rossi; F. Sforza; Franco Toto (HLDVT, 2002)

Evaluating a New RRAM Manufacturing Test Strategy. - Thiago Santos Copetti; A. Castelnuovo; Tobias Gemmeke; Letícia Maria Veiras Bolzani (LATS, 2023)