Design, Implementation and Performance of Fault-Tolerant Message Passing Interface (MPI). - A. David Selvakumar; P. M. Sobha; G. C. Ravindra; R. Pitchiah (PDCS, 2004)

SCADA with Fault Tolerant CORBA on Fault Tolerant LANE ATM. - A. David Selvakumar; Chester Rebeiro; R. Pitchiah (IPDPS, 2005)

Bitslice Implementation of AES. - Chester Rebeiro; A. David Selvakumar; A. S. L. Devi (CANS, 2006)

Wireless sensor node variants and their application domains. - Ramana Rao; Haribabu; David Selvakumar (ACWR, 2011)

Wireless sensor device hardware architecture - Design and analysis for high availability. - David Selvakumar; Kaushik Nanda; Hari Babu Pasupuleti (NTMS, 2015)

Out of order floating point coprocessor for RISC V ISA. - Vinayak Patil; Aneesh Raveendran; P. M. Sobha; A. David Selvakumar; Vivian Desalphine (VDAT, 2015)

RISC-V out-of-order data conversion co-processor. - Aneesh Raveendran; Vinayak Patil; Vivian Desalphine; P. M. Sobha; A. David Selvakumar (VDAT, 2015)

RISC-V Half Precision Floating Point Instruction Set Extensions and Co-processor. - Aneesh Raveendran; Sandra Jean; J. Mervin; Vivian Desalphine; A. David Selvakumar (VDAT, 2019)

Functional Simulation Verification of RISC-V Instruction Set Based High Level Language Modeled FPU. - Aneesh Raveendran; Vinay Kumar; Vivian Desalphine; David Selvakumar (VDAT, 2019)

Side Channel Leakage Assessment Strategy On Attack Resistant AES Architectures. - Shabbir Darbar; J. Mervin; David Selvakumar (VDAT, 2020)

Novel Method for Verification and Performance Evaluation of a Non-Blocking Level-1 Instruction Cache designed for Out-of-Order RISC-V Superscaler Processor on FPGA. - Vivian Desalphine; Somya Dashora; Laxita Mali; Suhas K; Aneesh Raveendran; David Selvakumar (VDAT, 2020)

A Novel Parametrized Fused Division and Square-Root POSIT Arithmetic Architecture. - Aneesh Raveendran; Sandra Jean; J. Mervin; Vivian Desalphine; David Selvakumar (VLSID, 2020)

Area-Time Scalable High Radix Montgomery Modular Multiplier for Large Modulus. - Venkata Reddy Kolagatla; Vivian Desalphine; David Selvakumar (VDAT, 2021)

A Randomized Montgomery Powering Ladder Exponentiation for Side-Channel Attack Resilient RSA and Leakage Assessment. - Venkata Reddy Kolagatla; J. Mervin; Shabbir Darbar; David Selvakumar; Sankha Saha (VDAT, 2021)

Formal Verification and Analysis of a Pseudo Random Number Generator. - David Selvakumar; J. Mervin; Shashikala Gunderao Pattanshetty; Vivian Desalphine (VDAT, 2021)

P-FMA: A Novel Parameterized Posit Fused Multiply-Accumulate Arithmetic Processor. - Sandra Jean; Aneesh Raveendran; A. David Selvakumar; Gagandeep Kaur; Shankar G. Dharani; Shashikala Gunderao Pattanshetty; Vivian Desalphine (VLSID, 2021)

PositGen-A Verification Suite for Posit Arithmetic. - Annarao Kulkarni; Shashikala Gunderao Pattanshetty; Aneesh Raveendran; David Selvakumar; Sandra Jean; Vivian Desalphine (VLSID, 2021)

Design and Analysis of Posit Quire Processing Engine for Neural Network Applications. - Pranose J. Edavoor; Aneesh Raveendran; David Selvakumar; Vivian Desalphine; Shankar G. Dharani; Gopal Raut (VLSID, 2023)

A SIMD Dynamic Fixed Point Processing Engine for DNN Accelerators. - Gopal Raut; Pranose J. Edavoor; David Selvakumar; Ritambhara Thakur (ISQED, 2024)