Sequential Machine Implementations Using Universal Logic Modules. - A. E. A. Almaini (IEEE Trans. Computers, 1978)

An introduction to microcomputer systems architecture and interfacing: Fulcher, J Addison-Wesley, Workingham, UK (1989) pp 425. - A. E. A. Almaini (Microprocess. Microsystems, 1990)

ASIC implementation of a programmable error-trapping decoder for binary codes of length 15. - A. E. A. Almaini; S. S. Aziz (Microprocess. Microsystems, 1990)

A Parallel CMOS 2's Complement Multiplier Based on 5: 3 Counter. - Z. Guan; P. Thomson; A. E. A. Almaini (ICCD, 1994)

Multilevel Logic Minimization Using Functional Don't Cares. - Lingli Wang; A. E. A. Almaini (VLSI Design, 2001)

Best Polarity for Low Power XOR Gate Decomposition. - Yinshui Xia; A. E. A. Almaini (DSD, 2002)

Area and power optimization of FPRM function based circuits. - Yinshui Xia; B. Ali; A. E. A. Almaini (ISCAS (5), 2003)

The Application of the Wavelet Transform to Polysomnographic Signals. - M. MacCallum; A. E. A. Almaini (Int. J. Wavelets Multiresolution Inf. Process., 2003)

Power Minimization of FPRM Functions Based on Polarity Conversion. - Yinshui Xia; Xunwei Wu; A. E. A. Almaini (J. Comput. Sci. Technol., 2003)

Evolutionary Algorithms and Theirs Use in the Design of Sequential Logic Circuits. - B. Ali; A. E. A. Almaini; Tatiana Kalganova (Genet. Program. Evolvable Mach., 2004)

A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock. - Yinshui Xia; Lun-Yao Wang; A. E. A. Almaini (J. Comput. Sci. Technol., 2005)

Fast Conversion for Large Canonical OR-Coincidence Functions. - Meng Yang 013; Lingli Wang; A. E. A. Almaini (APCCAS, 2006)

Techniques for dual forms of Reed-Muller expansion conversion. - Meng Yang 013; Lingli Wang; Jiarong Tong; A. E. A. Almaini (Integr., 2008)

Manipulation and optimisation techniques for Boolean logic. - B. A. Al Jassani; Neil Urquhart; A. E. A. Almaini (IET Comput. Digit. Tech., 2010)

State assignment for sequential circuits using multi-objective genetic algorithm. - B. A. Al Jassani; Neil Urquhart; A. E. A. Almaini (IET Comput. Digit. Tech., 2011)

Reed-Muller function optimization techniques with onset table. - Lun-Yao Wang; Yinshui Xia; Xiexiong Chen; A. E. A. Almaini (J. Zhejiang Univ. Sci. C, 2011)

Indirect connection aware attraction for FPGA clustering (abstract only). - Meng Yang 013; Jiarong Tong; A. E. A. Almaini (FPGA, 2013)

An Architecture Independent Packing Method for LUT-based Commercial FPGA. - Meng Yang 013; Jinmei Lai 001; A. E. A. Almaini (J. Comput., 2014)