Fractional-N DPLL based low power clocking architecture for 1-14 Gb/s multi-standard transmitter. - Masum Hossain; Amlan Nag; Waleed El-Halwagy; A. K. M. Delwar Hossain; Aurangozeb (A-SSCC, 2016)

A 35 mW 10 Gb/s ADC-DSP less direct digital sequence detector and equalizer in 65nm CMOS. - A. K. M. Delwar Hossain; Aurangozeb; Maruf Mohammad; Masum Hossain (VLSI Circuits, 2016)

A 82 mW 28 Gb/s PAM-4 digital sequence decoder with built-in error correction in 28nm FDSOI. - Masum Hossain; Aurangozeb; A. K. M. Delwar Hossain; Maruf Mohammad (A-SSCC, 2017)

Channel adaptive ADC and TDC for 28 Gb/s PAM-4 digital receiver. - Aurangozeb; A. K. M. Delwar Hossain; Masum Hossain (CICC, 2017)

Fractional-N DPLL-Based Low-Power Clocking Architecture for 1-14 Gb/s Multi-Standard Transmitter. - Masum Hossain; Waleed El-Halwagy; A. K. M. Delwar Hossain; Aurangozeb (IEEE J. Solid State Circuits, 2017)

Time-Domain Arithmetic Logic Unit With Built-In Interconnect. - Aurangozeb; A. K. M. Delwar Hossain; Can Ni; Quazi Sharar; Masum Hossain (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Burst Mode Optical Receiver With 10 ns Lock Time Based on Concurrent DC Offset and Timing Recovery Technique. - A. K. M. Delwar Hossain; Aurangozeb; Masum Hossain (JOCN, 2018)

Channel-Adaptive ADC and TDC for 28 Gb/s PAM-4 Digital Receiver. - Aurangozeb; A. K. M. Delwar Hossain; Maruf Mohammad; Masum Hossain (IEEE J. Solid State Circuits, 2018)