Transient-induced latch-up test setup for wafer-level and package-level. - Detlef Bonfert; Horst A. Gieser; Heinrich Wolf; M. Frank; A. Konrad; J. Schulz (Microelectron. Reliab., 2006)

Analysis of triggering behaviour of high voltage CMOS LDMOS clamps and SCRs during ESD induced latch-up. - Michael Heer; Viktor Dubec; Sergey Bychikhin; Dionyz Pogany; Erich Gornik; M. Frank; A. Konrad; J. Schulz (Microelectron. Reliab., 2006)