A 5 Gbps Wafer-Level Tester. - A. M. Majid; David C. Keezer; J. V. Karia (Asian Test Symposium, 2005)

Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL. - David C. Keezer; Carl Gray; Ashraf M. Majid; Nafeez Taher (DATE, 2005)

Implementing multi-gigahertz test systems using CMOS FPGAs and PECL components. - David C. Keezer; Carl Gray; Ashraf Majid; Nafeez Taher (ESSCIRC, 2005)

Multi-Gigahertz Testing of Wafer-Level Packaged Devices. - A. M. Majid; David C. Keezer; Jayasanker Jayabalan; Mihai Rotaru (ITC, 2006)

An Electronic Module for 12.8 Gbps Multiplexing and Loopback Test. - David C. Keezer; Dany Minier; Patrice Ducharme; A. M. Majid (ITC, 2008)

A development platform and electronic modules for automated test up to 20 Gbps. - David C. Keezer; Carl Gray; A. M. Majid; Dany Minier; Patrice Ducharme (ITC, 2009)

Stretching the limits of FPGA SerDes for enhanced ATE performance. - A. M. Majid; David C. Keezer (DATE, 2010)

Multi-function multi-GHz ATE extension using state-of-the-art FPGAs. - A. M. Majid; David C. Keezer (ITC, 2011)

Methods for extending high-performance automated test equipment (ATE) using multi-gigahertz FPGA technologies. - Ashraf M. Majid (2011)

Practical methods for extending ATE to 40 and 50Gbps. - David C. Keezer; Carl Edward Gray; Te-Hui Chen; Ashraf Majid (ITC, 2013)