Symbolic Simulation for the Verification of Temporal Logic Specifications about Sequential Designs. - A. Mete Kabakçioglu; Edward P. Stabler (Int. J. Comput. Simul., 1991)

DEVE: An Expert System for Hardware Design Verification. - A. Mete Kabakçioglu; Olga L. Mazuera (ICTAI, 1992)

CAN: chain of nodes approach to direct rule induction. - A. Mete Kabakçioglu (IEEE Trans. Syst. Man Cybern. Part B, 1999)