Quaternary High Performance Arithmetic Logic Unit Design. - A. N. Nagamani; S. Nishchai (DSD, 2011)

Progress in Reversible Processor Design: A Novel Methodology for Reversible Carry Look-Ahead Adder. - Himanshu Thapliyal; H. V. Jayashree; A. N. Nagamani; Hamid R. Arabnia (Trans. Comput. Sci., 2013)

Design of optimized reversible multiplier for high speed DSP application. - A. N. Nagamani; H. Vishnu Prasad; Rajendra S. Hathwar; Vinod Kumar Agrawal (ICICS, 2015)

Reversible Radix-4 booth multiplier for DSP applications. - A. N. Nagamani; R. Nikhil; Manish Nagaraj; Vinod Kumar Agrawal (SPCOM, 2016)

An Exact approach for Complete Test Set Generation of Toffoli-Fredkin-Peres based Reversible Circuits. - A. N. Nagamani; S. Ashwin; B. Abhishek; Vinod Kumar Agrawal (J. Electron. Test., 2016)

Design and Analysis of Multiple Parameters Optimized n-Bit Reversible Magnitude Comparators. - A. N. Nagamani; S. Ashwin; B. Abhishek; K. V. Arjun; Vinod Kumar Agrawal (J. Circuits Syst. Comput., 2016)

DFT methodologies for testing k-CNOT, Fredkin and Peres based reversible circuits. - A. N. Nagamani; Vijetha Ravichander; Madhumita Harish; Vinod Kumar Agrawal (RAIT, 2018)

Design of Optimized Reversible Squaring and Sum-of-Squares Units. - A. N. Nagamani; Chirag Ramesh; Vinod Kumar Agrawal (Circuits Syst. Signal Process., 2018)

A Genetic Algorithm-Based Heuristic Method for Test Set Generation in Reversible Circuits. - A. N. Nagamani; S. N. Anuktha; N. Nanditha; Vinod Kumar Agrawal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Hardware Security-present and Future Trends. - S. S. Rekha; A. N. Nagamani (EEET, 2019)