A Real Time, Low Latency, FPGA Implementation of the 2-D Discrete Wavelet Transformation for Streaming Image Applications. - Oguz Benderli; Yusuf Çagatay Tekmen; A. Neslin Ismailoglu (DSD, 2003)

A High Speed FPGA Implementation of the Rijndael Algorithm. - Refik Sever; A. Neslin Ismailoglu; Yusuf Çagatay Tekmen; Murat Askar; Burak Okcan (DSD, 2004)

A high speed ASIC implementation of the Rijndael algorithm. - Refik Sever; A. Neslin Ismailoglu; Yusuf Çagatay Tekmen; Murat Askar (ISCAS (2), 2004)

Two fast RSA implementations using high-radix montgomery algorithm. - Soner Yesil; A. Neslin Ismailoglu; Yusuf Çagatay Tekmen; Murat Askar (ISCAS (2), 2004)

Improving compression ratio for satellite transmission by use of cloud extraction. - Rusen Öktem; Oguz Benderli; A. Neslin Ismailoglu (EUSIPCO, 2005)

GEZGIN & GEZGIN-2: Adaptive Real-Time Image Processing Subsystems for Earth Observing Small Satellites. - A. Neslin Ismailoglu; Oguz Benderli; Soner Yesil; Refik Sever; Burak Okcan; O. Sengul; Rusen Öktem (AHS, 2006)

Application of Bit-level Pipelining to Delay Insensitive Null Convention Adders. - A. Neslin Ismailoglu; Murat Askar (ISCAS, 2007)

SDIVA: Structural Delay Insensitivity Verification Analysis Method for Bit-Level Pipelined Systolic Arrays with Early Output Evaluation. - A. Neslin Ismailoglu; Murat Askar (DSD, 2008)

Delay insensitivity verification of bit-level pipelined systolic arrays in dual-rail treshold logic. - Ayse Neslin Ismailoglu; Murat Askar (ICECS, 2008)

Asynchronous design of systolic array architectures in cmos ; cmos devrelerle asenkron sistolik dizi mimarisi tasarımı. - Ayse Neslin Ismailoglu (2008)