A New Delay Model and Geometric Programming-Based Design Automation for Latched Comparators. - A. Purushothaman; Chetan D. Parikh (Circuits Syst. Signal Process., 2015)

A low power low area capacitor array based Digital to Analog Converter architecture. - A. Purushothaman; Chetan D. Parikh (Microelectron. J., 2015)

MINLP Based Power Optimization for Pipelined ADC. - A. Purushothaman (ISVLSI, 2016)

Analysis of regeneration time constant of dynamic latch using Adomian Decomposition method. - A. Purushothaman (VDAT, 2016)

Assessing the Performance of CMOS Amplifiers Using High-k Dielectric with Metal Gate on High Mobility Substrate. - Deepa Anand; M. Swathi; A. Purushothaman; Sundararaman Gopalan (ICACDS (1), 2018)

Mitigating Aperture Error in Pipelined ADCs Without a Front-end Sample-and-Hold Amplfier. - Diego James; Abishek T. Kunnath; A. Purushothaman; Bibhudatta Sahoo 002 (VLSID, 2018)

Geometric Programming-Based Power Optimization and Design Automation for a Digitally Controlled Pulse Width Modulator. - P. Rajeswari; G. Shekar; S. Devi; A. Purushothaman (Circuits Syst. Signal Process., 2018)

Brain Inspired One Shot Learning Method for HD Computing. - Devika R. Nair; A. Purushothaman (VDAT, 2019)

Deep Learning Based Approach for Hardware Trojan Detection. - Sriram Sankaran; Vamshi Sunku Mohan; A. Purushothaman (iSES, 2021)