Fast and Efficient On-Chip Interconnection Delay Modeling for High Speed VLSI Systems. - A. R. Aswatha; T. G. Basavaraju; Subir Kumar Sarkar (ICETET, 2008)

Design and Analysis of a New Loadless 4T SRAM Cell in Deep Submicron CMOS Technologies. - Sandeep R. 001; Narayan T. Deshpande; A. R. Aswatha (ICETET, 2009)