High Level Design Experiences with IDEAS. - C. S. Ajay; M. Balakrishnan; D. Harikrishna; M. Karunakaran; Anshul Kumar; Shashi Kumar; V. Mudgil; A. R. Naseer (VLSI Design, 1993)

An Efficient Technique for Mapping RTL Structures onto FPGAs. - A. R. Naseer; M. Balakrishnan; Anshul Kumar (FPL, 1994)

FAST: FPGA Targeted RTL Structure Synthesis Technique. - A. R. Naseer; M. Balakrishnan; Anshul Kumar (VLSI Design, 1994)

Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs. - A. R. Naseer; M. Balakrishnan; Anshul Kumar (FPL, 1995)

Optimal Clock Period for Synthesized Data Paths. - A. R. Naseer; M. Balakrishnan; Anshul Kumar (VLSI Design, 1997)

Direct mapping of RTL structures onto LUT-based FPGA's. - A. R. Naseer; M. Balakrishnan; Anshul Kumar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

SNARE: sensor node attached reputation evaluator. - Ismat K. Maarouf; A. R. Naseer (CoNEXT, 2006)

WSNodeRater - An Optimized Reputation System Framework for Security Aware Energy Efficient Geographic Routing in WSNs. - Ismat K. Maarouf; A. R. Naseer (AICCSA, 2007)

Two-way distributed sequential pattern mining using fruit fly algorithm along with Hadoop and map reduce framework. - V. Malsoru; A. R. Naseer; G. Narsimha (Int. J. Comput. Aided Eng. Technol., 2021)