High-Level Synthesis from VHDL with Exact Timing Constraints. - A. Stoll; Peter Duzy (DAC, 1992)

Flexible timing specification in a VHDL synthesis subset. - A. Stoll; Jörg Biesenack; Steffen Rumler (EURO-DAC, 1992)

Data Part Optimizations in the CALLAS Synthesis Environment. - Jörg Biesenack; Norbert Wehn; A. Stoll; Michael Payer (Synthesis for Control Dominated Circuits, 1992)