Design of a Novel Reversible Full Adder and Reversible Full Subtractor. - A. V. AnanthaLakshmi; G. Florence Sudha (ACITY (3), 2012)

Transistor Representation of a Low-Power Reversible 32-Bit Comparator. - A. V. AnanthaLakshmi; G. Florence Sudha (ICACNI, 2013)

Design of an efficient reversible single precision floating point adder. - A. V. AnanthaLakshmi; G. Florence Sudha (Int. J. Comput. Intell. Stud., 2015)

A novel power efficient 0.64-GFlops fused 32-bit reversible floating point arithmetic unit architecture for digital signal processing applications. - A. V. AnanthaLakshmi; Gnanou Florence Sudha (Microprocess. Microsystems, 2017)

Design of a reversible floating-point square root using modified non-restoring algorithm. - A. V. AnanthaLakshmi; Gnanou Florence Sudha (Microprocess. Microsystems, 2017)

Approximate subtractors designed for image processing applications. - P. Divya Parameswari; A. V. AnanthaLakshmi (Integr., 2025)