Hyperchaos in a Modified Canonical Chua's Circuit. - Kathamuthu Thamilmaran; M. Lakshmanan 001; A. Venkatesan (Int. J. Bifurc. Chaos, 2004)

Classification of bifurcations and Chaos in Chua's Circuit with Effect of Different Periodic Forces. - K. Srinivasan 001; Kathamuthu Thamilmaran; A. Venkatesan (Int. J. Bifurc. Chaos, 2009)

Vibrational resonance and implementation of dynamic logic gate in a piecewise-linear Murali-Lakshmanan-Chua circuit. - P. R. Venkatesh; A. Venkatesan (Commun. Nonlinear Sci. Numer. Simul., 2016)

Chimera at the phase-flip transition of an ensemble of identical nonlinear oscillators. - R. Gopal; V. K. Chandrasekar; D. V. Senthilkumar; A. Venkatesan; M. Lakshmanan 001 (Commun. Nonlinear Sci. Numer. Simul., 2018)

Realization of all logic gates and memory latch in the SC-CNN cell of the simple nonlinear MLC circuit. - P. Ashokkumar; M. Sathish Aravindh; A. Venkatesan; M. Lakshmanan 001 (CoRR, 2021)

Diode Connected Transistor-Based Low PDP Adiabatic Full Adder in 7 nm FINFET Technology for MIMO Applications. - A. Venkatesan; P. T. Vanathi; M. Elangovan (J. Circuits Syst. Comput., 2023)

Erratum: Diode Connected Transistor-Based Low PDP Adiabatic Full Adder in 7nm FINFET Technology for MIMO Applications. - A. Venkatesan; P. T. Vanathi; M. Elangovan (J. Circuits Syst. Comput., 2023)

Reservoir computing with logistic map. - R. Arun; M. Sathish Aravindh; A. Venkatesan; M. Lakshmanan 001 (CoRR, 2024)