Predicting the Performance of a 3D Processor-Memory Chip Stack. - Philip Jacob 001; Okan Erdogan; Aamir Zia; Paul M. Belemjian; Russell P. Kraft; John F. McDonald 001 (IEEE Des. Test Comput., 2005)

Amdahl's figure of merit, SiGe HBT BiCMOS, and 3D chip stacking. - Philip Jacob 001; Aamir Zia; Okan Erdogan; Paul M. Belemjian; Peng Jin; Jin Woo Kim; Michael Chu; Russell P. Kraft; John F. McDonald 001 (ICCD, 2007)

Thermal analysis for a SiGe HBT 40 watt 32 GHz clock 3D memory processor chip stack using diamond heat spreader layers. - John F. McDonald 001; Okan Erdogan; Philip Jacob 001; Paul M. Belemjian; Alexey Gutin; Aamir Zia; Michael Chu; Jin Woo Kim; Ryan Clarke; Nate DeSimone; Sherry Liu; Russell P. Kraft (3DIC, 2009)

Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks. - Philip Jacob 001; Aamir Zia; Okan Erdogan; Paul M. Belemjian; Jin Woo Kim; Michael Chu; Russell P. Kraft; John F. McDonald 001; Kerry Bernstein (Proc. IEEE, 2009)

A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration. - Aamir Zia; Philip Jacob 001; Jin Woo Kim; Michael Chu; Russell P. Kraft; John F. McDonald 001 (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Reconfigurable 40 GHz BiCMOS uniform delay crossbar switch for broadband and wide tuning range narrowband applications. - Jin Woo Kim; Michael Chu; Philip Jacob 001; Aamir Zia; Russell P. Kraft; John F. McDonald 001 (IET Circuits Devices Syst., 2011)

3D NOC for many-core processors. - Aamir Zia; Sachhidh Kannan; H. Jonathan Chao; Garrett S. Rose (Microelectron. J., 2011)

A three-dimensional DRAM using floating body cell in FDSOI devices. - Xuelian Liu; Aamir Zia; Mitchell R. LeRoy; Srikumar Raman; Ryan Clarke; Russell P. Kraft; John F. McDonald 001 (DDECS, 2012)

Design of BiCMOS SRAMs for high-speed SiGe applications. - Xuelian Liu; Mitchell R. LeRoy; Ryan Clarke; Michael Chu; H. O. Aquino; Srikumar Raman; Aamir Zia; Russell P. Kraft; John F. McDonald 001 (IET Circuits Devices Syst., 2014)