FAE: Autoencoder-Based Failure Binning of RTL Designs for Verification and Debugging. - Cheng-Hsien Shen; Aaron C.-W. Liang; Charles C.-H. Hsu; Charles H.-P. Wen (ITC, 2019)

Speeding Up Functional Timing Analysis by Concise Formulation of Timed Characteristic Functions. - Denny C.-Y. Wu; Aaron C.-W. Liang; Charles H.-P. Wen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Generating Layouts of Standard Cells by Implicit Learning on Design Rules for Advanced Processes. - Aaron C.-W. Liang; Hsuan-Ming Huang; Charles H.-P. Wen (DATE, 2021)

Timing-Critical Path Analysis in Circuit Designs Considering Aging with Signal Probability. - Jiun-Cheng Tsai; Aaron C.-W. Liang; Charles H.-P. Wen (ITC-Asia, 2022)

Existence of Single-Event Double-Node Upsets (SEDU) in Radiation-Hardened Latches for Sub-65nm CMOS Technologies. - Sam M.-H. Hsiao; Lowry P.-T. Wang; Aaron C.-W. Liang; Charles H.-P. Wen (ITC, 2022)

SlewFTA: Functional Timing Analysis Considering Slew Propagation. - Zong-Hua Tsai; Aaron C.-W. Liang; Charles H.-P. Wen (VLSI-DAT, 2022)

A General and Automatic Cell Layout Generation Framework With Implicit Learning on Design Rules. - Aaron C.-W. Liang; Charles H.-P. Wen; Hsuan-Ming Huang (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Preventing Single-Event Double-Node Upsets by Engineering Change Order in Latch Designs. - Sam M.-H. Hsiao; Amy H.-Y. Tsai; Lowry P.-T. Wang; Aaron C.-W. Liang; Charles H.-P. Wen; Herming Chiueh (ITC, 2023)

MAXCell: PPA-Directed Multi-Height Cell Layout Routing Optimization using Anytime MaXSAT with Constraint Learning. - Jiun-Cheng Tsai; Wei-Min Hsu; Yun-Ting Hsieh; Yu-Ju Li; Wei Huang; C. N. Ho; Hsuan-Ming Huang; Jen-Hang Yang; Heng-Liang Huang; Aaron C.-W. Liang; Charles H.-P. Wen (ICCAD, 2024)

Machine-Learning-Based Ranking of Cell Layout Delay Considering Layout-Dependent Effects. - Ya-Rou Hsu; Aaron C.-W. Liang; Han-Ya Tsai; Yen-Ju Su; Charles H.-P. Wen; Hsuan-Ming Huang (IEEE Trans. Very Large Scale Integr. Syst., 2025)