Computer Modeling of Silicon Quantum Dot Floating -Gate Flash Memory Devices - Aaron Thean (2001)

Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacks. - Romain Ritzenthaler; Tom Schram; Erik Bury; Jérôme Mitard; L.-Å. Ragnarsson; Guido Groeseneken; N. Horiguchi; Aaron Thean; Alessio Spessot; Christian Caillat; V. Srividya; Pierre Fazan (ESSDERC, 2012)

Low-frequency noise assessment of the transport mechanisms in SiGe channel bulk FinFETs. - Tommaso Romeo; Luigi Pantisano; Eddy Simoen; Raymond Krom; Mitsuhiro Togo; N. Horiguchi; Jérôme Mitard; Aaron Thean; Guido Groeseneken; Cor Claeys; Felice Crupi (ESSDERC, 2012)

Impact of Al2O3 position on performances and reliability in high-k metal gated DRAM periphery transistors. - Marc Aoulaiche; Eddy Simoen; Romain Ritzenthaler; Tom Schram; Hiroaki Arimura; Moonju Cho; Thomas Kauerauf; Guido Groeseneken; Naoto Horiguchi; Aaron Thean; Antonio Federico; Felice Crupi; et al. (ESSDERC, 2013)

Design Technology co-optimization for N10. - Julien Ryckaert; Praveen Raghavan; Rogier Baert; Marie Garcia Bardon; Mircea Dusa; Arindam Mallik; Sushil Sakhare; Boris Vandewalle; Piet Wambacq; Bharani Chava; Kris Croes; Morin Dehan; et al. (CICC, 2014)

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies. - Trong Huynh Bao; Dmitry Yakimets; Julien Ryckaert; Ivan Ciofi; Rogier Baert; Anabela Veloso; Jürgen Bömmels; Nadine Collaert; Philippe Roussel; S. Demuynck; Praveen Raghavan; Abdelkarim Mercha; et al. (ESSDERC, 2014)

System-level assessment and area evaluation of Spin Wave logic circuits. - Odysseas Zografos; Praveen Raghavan; Luca Gaetano Amarù; Bart Soree; Rudy Lauwereins; Iuliana P. Radu; Diederik Verkest; Aaron Thean (NANOARCH, 2014)

Determination of energy and spatial distribution of oxide border traps in In0.53Ga0.47As MOS capacitors from capacitance-voltage characteristics measured at various temperatures. - Chunmeng Dou; Dennis Lin; Abhitosh Vais; Tsvetan Ivanov; Han-Ping Chen; Koen Martens; Kuniyuki Kakushima; Hiroshi Iwai; Yuan Taur; Aaron Thean; Guido Groeseneken (Microelectron. Reliab., 2014)

A digital intensive circuit for low-frequency noise monitoring in 28nm CMOS. - Bertrand Parvais; Piet Wambacq; Abdelkarim Mercha; Diederik Verkest; Aaron Thean; Ken Sawada; Kazuki Nomoto; Tetsuya Oishi; Hiroaki Ammo (A-SSCC, 2015)

Holisitic device exploration for 7nm node. - Praveen Raghavan; Marie Garcia Bardon; Doyoung Jang; P. Schuddinck; Dmitry Yakimets; Julien Ryckaert; Abdelkarim Mercha; Naoto Horiguchi; Nadine Collaert; Anda Mocuta; Dan Mocuta; Zsolt Tokei; et al. (CICC, 2015)

Characterization and simulation methodology for time-dependent variability in advanced technologies. - Pieter Weckx; Ben Kaczer; Praveen Raghavan; Jacopo Franco; Marko Simicic; Philippe J. Roussel; Dimitri Linten; Aaron Thean; Diederik Verkest; Francky Catthoor; Guido Groeseneken (CICC, 2015)

Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM. - Trong Huynh Bao; Sushil Sakhare; Julien Ryckaert; Dmitry Yakimets; Abdelkarim Mercha; Diederik Verkest; Aaron Voon-Yew Thean; Piet Wambacq (ICICDT, 2015)

Dimensioning for power and performance under 10nm: The limits of FinFETs scaling. - Marie Garcia Bardon; P. Schuddinck; Praveen Raghavan; Doyoung Jang; Dmitry Yakimets; Abdelkarim Mercha; Diederik Verkest; Aaron Thean (ICICDT, 2015)

FinFET stressor efficiency on alternative wafer and channel orientations for the 14 nm node and below. - Geert Eneman; An De Keersgieter; Anda Mocuta; Nadine Collaert; Aaron Thean (ICICDT, 2015)

Impact of device and interconnect process variability on clock distribution. - Nathalie Fievet; Praveen Raghavan; Rogier Baert; Frédéric Robert; Abdelkarim Mercha; Diederik Verkest; Aaron Thean (ICICDT, 2015)

Modeling FinFET metal gate stack resistance for 14nm node and beyond. - Kenichi Miyaguchi; Bertrand Parvais; Lars-Åke Ragnarsson; Piet Wambacq; Praveen Raghavan; Abdelkarim Mercha; Anda Mocuta; Diederik Verkest; Aaron Thean (ICICDT, 2015)

Nonparabolicity and confinement effects of IIIV materials in novel transistors. - M. Ali Pourghaderi; Anda Mocuta; Aaron Thean (ICICDT, 2015)

I/O thick oxide device integration using Diffusion and Gate Replacement (D&GR) gate stack integration. - Romain Ritzenthaler; Tom Schram; M. J. Cho; Anda Mocuta; Naoto Horiguchi; Aaron Voon-Yew Thean; Alessio Spessot; Christian Caillat; Marc Aoulaiche; Pierre Fazan; K. B. Noh; Y. Son (ICICDT, 2015)

Assessment of SiGe quantum well transistors for DRAM peripheral applications. - Romain Ritzenthaler; Tom Schram; Geert Eneman; Anda Mocuta; Naoto Horiguchi; Aaron Voon-Yew Thean; Alessio Spessot; Marc Aoulaiche; Pierre Fazan; K. B. Noh; Y. Son (ICICDT, 2015)

Impact of fin shape variability on device performance towards 10nm node. - Kazuyuki Tomida; Keizo Hiraga; Morin Dehan; Geert Hellings; Doyoung Jang; Kenichi Miyaguchi; Thomas Chiarella; Minsoo Kim; Anda Mocuta; Naoto Horiguchi; Abdelkarim Mercha; Diederik Verkest; et al. (ICICDT, 2015)

Lateral NWFET optimization for beyond 7nm nodes. - Dmitry Yakimets; Doyoung Jang; Praveen Raghavan; Geert Eneman; Hans Mertens; P. Schuddinck; Arindam Mallik; Marie Garcia Bardon; Nadine Collaert; Abdelkarim Mercha; Diederik Verkest; Aaron Thean; et al. (ICICDT, 2015)

Area and routing efficiency of SWD circuits compared to advanced CMOS. - Odysseas Zografos; Praveen Raghavan; Yasser Sherazi; Adrien Vaysset; Florin Ciubotaru; Bart Soree; Rudy Lauwereins; Iuliana P. Radu; Aaron Thean (ICICDT, 2015)

NBTI in Si0.55Ge0.45 cladding p-FinFETs: Porting the superior reliability from planar to 3D architectures. - Jacopo Franco; Ben Kaczer; Philippe J. Roussel; Erik Bury; Hans Mertens; Romain Ritzenthaler; Tibor Grasser; Naoto Horiguchi; Aaron Thean; Guido Groeseneken (IRPS, 2015)

Origins and implications of increased channel hot carrier variability in nFinFETs. - Ben Kaczer; Jacopo Franco; M. Cho; Tibor Grasser; Philippe J. Roussel; Stanislav Tyaginov; M. Bina; Yannick Wimmer; Luis-Miguel Procel; Lionel Trojman; Felice Crupi; Gregory Pitner; et al. (IRPS, 2015)

The relationship between border traps characterized by AC admittance and BTI in III-V MOS devices. - Abhitosh Vais; Koen Martens; Jacopo Franco; Dennis Lin; AliReza Alian; Philippe Roussel; S. Sioncke; Nadine Collaert; Aaron Thean; Marc M. Heyns; Guido Groeseneken; Kristin De Meyer (IRPS, 2015)

Active-lite interposer for 2.5 & 3D integration. - Geert Hellings; Mirko Scholz; Mikael Detalle; Dimitrios Velenis; Muriel de Potter de ten Broeck; C. Roda Neve; Y. Li; Stefaan Van Huylenbroeck; Shih-Hung Chen; Erik Jan Marinissen; Antonio La Manna; Geert Van der Plas; et al. (VLSIC, 2015)

Effect of material parameters on two-dimensional materials based TFETs: An energy-delay perspective. - Tarun Agarwal; Iuliana P. Radu; Praveen Raghavan; Gianluca Fiori; Aaron Thean; Marc M. Heyns; Wim Dehaene (ESSCIRC, 2016)

Towards high performance sub-10nm finW bulk FinFET technology. - Thomas Chiarella; Stefan Kubicek; E. Rosseel; Romain Ritzenthaler; Andriy Hikavyy; P. Eyben; An De Keersgieter; L.-Å. Ragnarsson; M.-S. Kim; S.-A. Chew; Tom Schram; S. Demuynck; et al. (ESSDERC, 2016)

Non-uniform strain in lattice-mismatched heterostructure tunnel field-effect transistors. - Devin Verreck; Anne S. Verhulst; Bart Soree; Nadine Collaert; Anda Mocuta; Aaron Thean; Guido Groeseneken (ESSDERC, 2016)

Beyond-Si materials and devices for more Moore and more than Moore applications. - Nadine Collaert; AliReza Alian; Hiroaki Arimura; Geert Boccardi; Geert Eneman; Jacopo Franco; Tsvetan Ivanov; Dennis Lin; Jérôme Mitard; S. Ramesh; R. Rooyackers; Marc Schaekers; et al. (ICICDT, 2016)

Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs. - Bon Woong Ku; Peter Debacker; Dragomir Milojevic; Praveen Raghavan; Diederik Verkest; Aaron Thean; Sung Kyu Lim (ISLPED, 2016)

5nm: Has the time for a device change come? - Praveen Raghavan; Marie Garcia Bardon; Peter Debacker; P. Schuddinck; Doyoung Jang; Rogier Baert; Diederik Verkest; Aaron Voon-Yew Thean (ISQED, 2016)

Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond. - Trong Huynh Bao; Julien Ryckaert; Zsolt Tokei; Abdelkarim Mercha; Diederik Verkest; Aaron Voon-Yew Thean; Piet Wambacq (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A 7×7×2mm3 8.6-μ 500-kb/s Transmitter with Robust Injection-Locking Based Frequency-to-Amplitude Conversion Receiver Targeting for Implantable Applications. - Bo Xiong; Yida Li; Aaron Voon-Yew Thean; Chun-Huat Heng (CICC, 2019)

Design of Artificial Spiking Neuron with SiO2 Memristive Synapse to Demonstrate Neuron-Level Spike Timing Dependent Plasticity. - Jessie Xuhua Niu; Hasita Veluri; Yida Li; Umesh Chand; Jin Feng Leong; Evgeny Zamburg; Maheswari Sivan; Aaron Voon-Yew Thean (ICICDT, 2019)

Fledge: Flexible Edge Platforms Enabled by In-memory Computing. - Kamalika Datta; Arko Dutt; Ahmed Zaky; Umesh Chand; Devendra Singh; Yida Li; Jackson Chun-Yang Huang; Aaron Thean; Mohamed M. Sabry Aly (DATE, 2020)

Quantifying the Benefits of Monolithic 3D Computing Systems Enabled by TFT and RRAM. - Abdallah M. Felfel; Kamalika Datta; Arko Dutt; Hasita Veluri; Ahmed Zaky; Aaron Voon-Yew Thean; Mohamed M. Sabry Aly (DATE, 2020)

Seal Integrity Testing Utilizing Non-Destructive Capacitive Sensing for Product Packaging Assurance. - Jieming Pan; Yida Li; Yuxuan Luo; Xiangyu Zhang; Zaifeng Yang; David Liang Tai Wong; Jessie Xuhua Niu; Chen-Khong Tham; Aaron Voon-Yew Thean (IEEE SENSORS, 2020)

23.2 A 70µW 1.19mm2 Wireless Sensor with 32 Channels of Resistive and Capacitive Sensors and Edge-Encoded PWM UWB Transceiver. - Yuxuan Luo; Yida Li; Aaron Voon-Yew Thean; Chun-Huat Heng (ISSCC, 2020)

An 8.2- $ mu$ W 0.14-mm2 16-Channel CDMA-Like Capacitance-to-Digital Converter. - Yuxuan Luo; Yida Li; Aaron Voon-Yew Thean; Chun-Huat Heng (IEEE J. Solid State Circuits, 2020)

A $7 times7 times2$ mm3 8.6- $ mu$ W 500-kb/s Transmitter With Robust Injection-Locking-Based Frequency-to-Amplitude Conversion Receiver Targeting for Implantable Applications. - Bo Xiong; Yida Li; Aaron Voon-Yew Thean; Chun-Huat Heng (IEEE J. Solid State Circuits, 2020)

A Wireless Multi-Channel Capacitive Sensor System for Efficient Glove-Based Gesture Recognition With AI at the Edge. - Jieming Pan; Yuxuan Luo; Yida Li; Chen-Khong Tham; Chun-Huat Heng; Aaron Voon-Yew Thean (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

High-Throughput, Area-Efficient, and Variation-Tolerant 3-D In-Memory Compute System for Deep Convolutional Neural Networks. - Hasita Veluri; Yida Li; Jessie Xuhua Niu; Evgeny Zamburg; Aaron Voon-Yew Thean (IEEE Internet Things J., 2021)

A 70-μW 1.35-mm2 Wireless Sensor With 32 Channels of Resistive and Capacitive Sensors and Edge-Encoded PWM UWB Transceiver. - Yuxuan Luo; Yida Li; Aaron Voon-Yew Thean; Chun-Huat Heng (IEEE J. Solid State Circuits, 2021)

Sub-10nm Ultra-thin ZnO Channel FET with Record-High 561 µA/µm ION at VDS 1V, High µ-84 cm2/V-s and1T-1RRAM Memory Cell Demonstration Memory Implications for Energy-Efficient Deep-Learning Computing. - Umesh Chand; Mohamed M. Sabry Aly; Manohar Lal; Chen Chun-Kuei; Sonu Hooda; Shih-Hao Tsai; Zihang Fang; Hasita Veluri; Aaron Voon-Yew Thean (VLSI Technology and Circuits, 2022)

A Wafer Scale Hybrid Integration Platform for Co-packaged Photonics using a CMOS based Optical InterposerTM. - Suresh Venkatesan; James Lee; Simon Chun Kiat Goh; Brian Pile; Daniel Meerovich; Jinyu Mo; Yang Jing; Lucas Soldano; Baochang Xu; Yu Zhang; Aaron Voon-Yew Thean; Yeow Kheng Lim (VLSI Technology and Circuits, 2022)

Significance of activation functions in developing an online classifier for semiconductor defect detection. - Md Meftahul Ferdaus; Bangjian Zhou; Ji Wei Yoon; Kain Lu Low; Jieming Pan; Joydeep Ghosh; Min Wu 008; Xiaoli Li 001; Aaron Voon-Yew Thean; J. Senthilnath 001 (Knowl. Based Syst., 2022)

Quantile Online Learning for Semiconductor Failure Analysis. - Bangjian Zhou; Jieming Pan; Maheswari Sivan; Aaron Voon-Yew Thean; J. Senthilnath 001 (ICASSP, 2023)

Overcoming Negative nFET VTH by Defect-Compensated Low-Thermal Budget ITO-IGZO Hetero-Oxide Channel to Achieve Record Mobility and Enhancement-mode Operation. - Sonu Hooda; Chun-Kuei Chen; Manohar Lal; Shih-Hao Tsai; Evgeny Zamburg; Aaron Voon-Yew Thean (VLSI Technology and Circuits, 2023)

A Low-Power DNN Accelerator Enabled by a Novel Staircase RRAM Array. - Hasita Veluri; Umesh Chand; Yida Li; Baoshan Tang; Aaron Voon-Yew Thean (IEEE Trans. Neural Networks Learn. Syst., 2023)

A Low-Latency DNN Accelerator Enabled by DFT-Based Convolution Execution Within Crossbar Arrays. - Hasita Veluri; Umesh Chand; Chun-Kuei Chen; Aaron Voon-Yew Thean (IEEE Trans. Neural Networks Learn. Syst., 2025)