Integrated flow for reverse engineering of nanoscale technologies. - Bernhard Lippmann; Michael Werner; Niklas Unverricht; Aayush Singla; Peter Egger; Anja Dübotzky; Horst A. Gieser; Martin Rasche; Oliver Kellermann; Helmut Graeb (ASP-DAC, 2019)

Verification of Physical Chip Layouts Using GDSII Design Data. - Aayush Singla; Bernhard Lippmann; Helmut Graeb (IVSW, 2019)

Recovery of 2D and 3D Layout Information through an Advanced Image Stitching Algorithm using Scanning Electron Microscope Images. - Aayush Singla; Bernhard Lippmann; Helmut Graeb (ICPR, 2020)

Verification of physical designs using an integrated reverse engineering flow for nanoscale technologies. - Bernhard Lippmann; Niklas Unverricht; Aayush Singla; Matthias Ludwig 005; Michael Werner; Peter Egger; Anja Dübotzky; Helmut Gräb; Horst A. Gieser; Martin Rasche; Oliver Kellermann (Integr., 2020)