A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach. - Ivan Miro Panades; Alain Greiner; Abbas Sheibanyrad (Nano-Net, 2006)

Two Efficient Synchronous Û Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures. - Abbas Sheibanyrad; Alain Greiner (PATMOS, 2006)

Hybrid-Timing FIFOs to Use on Networks-on-Chip in GALS Architectures. - Abbas Sheibanyrad; Alain Greiner (ESA, 2007)

Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture. - Abbas Sheibanyrad; Ivan Miro Panades; Alain Greiner (DATE, 2007)

Multisynchronous and Fully Asynchronous NoCs for GALS Architectures. - Abbas Sheibanyrad; Alain Greiner; Ivan Miro Panades (IEEE Des. Test Comput., 2008)

Two efficient synchronous <–> asynchronous converters well-suited for networks-on-chip in GALS architectures. - Abbas Sheibanyrad; Alain Greiner (Integr., 2008)

Physical Implementation of an Asynchronous 3D-NoC Router Using Serial Vertical Links. - Florian Darve; Abbas Sheibanyrad; Pascal Vivet; Frédéric Pétrot (ISVLSI, 2011)

Asynchronous 3D-NoCs Making Use of Serialized Vertical Links. - Abbas Sheibanyrad; Frédéric Pétrot (3D Integration for NoC-based SoC Architectures, 2011)

Cost-efficient buffer sizing in shared-memory 3D-MPSoCs using wide I/O interfaces. - Sahar Foroutan; Abbas Sheibanyrad; Frédéric Pétrot (DAC, 2012)

A 3D-NoC Router Implementation Exploiting Vertically-Partially-Connected Topologies. - Maryam Bahmani; Abbas Sheibanyrad; Frédéric Pétrot; Florentine Dubois; Paolo Durante (ISVLSI, 2012)

Elevator-First: A Deadlock-Free Distributed Routing Algorithm for Vertically Partially Connected 3D-NoCs. - Florentine Dubois; Abbas Sheibanyrad; Frédéric Pétrot; Maryam Bahmani (IEEE Trans. Computers, 2013)

Assignment of Vertical-Links to Routers in Vertically-Partially-Connected 3-D-NoCs. - Sahar Foroutan; Abbas Sheibanyrad; Frédéric Pétrot (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

A Distributed NUCA Architecture Using an Efficient NoC Multicasting Support. - Hela Belhadj Amor; Abbas Sheibanyrad; Frédéric Pétrot (DSD, 2017)

A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links. - Pascal Vivet; Yvain Thonnart; Romain Lemaire; Cristiano Santos; Edith Beigné; Christian Bernard; Florian Darve; Didier Lattard; Ivan Miro Panades; Denis Dutoit; Fabien Clermidy; Séverine Cheramy; et al. (IEEE J. Solid State Circuits, 2017)