Systolic algorithms for tree pattern matching. - Abdel Ejnioui; N. Ranganathan (ICCD, 1995)

Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems. - Abdel Ejnioui; N. Ranganathan (FPGA, 1999)

A tree-matching chip. - Vamsi Krishna; N. Ranganathan; Abdel Ejnioui (IEEE Trans. Very Large Scale Integr. Syst., 1999)

Design Partitioning on Single-Chip Emulation Systems. - Abdel Ejnioui; N. Ranganathan (VLSI Design, 2000)

Routing on Switch Matrix Multi-FPGA Systems. - Abdel Ejnioui; N. Ranganathan (VLSI Design, 2000)

A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems. - Abdel Ejnioui; N. Ranganathan (IEEE Trans. Very Large Scale Integr. Syst., 2001)

A VLSI Architecture for Object Recognition Using Tree Matching. - K. Sitaraman; N. Ranganathan; Abdel Ejnioui (ASAP, 2002)

Supply Voltage Scalable System Design Using Self-Timed Circuits. - W. Kuang; J. S. Yuan; Abdel Ejnioui (ISVLSI, 2003)

Multiterminal net routing for partial crossbar-based multi-FPGA systems. - Abdel Ejnioui; N. Ranganathan (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Routing on field-programmable switch matrices. - Abdel Ejnioui; N. Ranganathan (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Pipeline-Level Control of Self-Resetting Pipelines. - Abdel Ejnioui; Abdelhalim Alsharqawi (DSD, 2004)

Self-resetting stage logic pipelines. - Abdel Ejnioui; Abdelhalim Alsharqawi (ACM Great Lakes Symposium on VLSI, 2004)

Pipeline Design Based on Self-Resetting Stage Logic. - Abdel Ejnioui; Abdelhalim Alsharqawi (ISVLSI, 2004)

A Reconfigurable Memory Management Core for Java Applications. - Abdel Ejnioui; Abdelkader Rhiati (ISVLSI, 2004)

Control and Data Flow Graph Extraction for High-Level Synthesis. - Ravi Namballa; Nagarajan Ranganathan; Abdel Ejnioui (ISVLSI, 2004)

Area Reclamation Strategies and Metrics for SRAM-Based Reconfigurable Devices. - Abdel Ejnioui; Ronald F. DeMara (ERSA, 2005)

SRSL pipelining of coarse-grain datapaths. - Abdelhalim Alsharqawi; Abdel Ejnioui (ICECS, 2005)

Pipeline synthesis of SRSL circuits. - Rashad S. Oreifej; Abdelhalim Alsharqawi; Abdel Ejnioui (ICECS, 2005)

Synthesis of Self-Resetting Stage Logic Pipelines. - Abdelhalim Alsharqawi; Abdel Ejnioui (ISVLSI, 2005)

Pipelining of double precision floating point division and square root operations. - Anuja Jayraj Thakkar; Abdel Ejnioui (ACM Southeast Regional Conference, 2006)

Complexity and Performance Evaluation of Two Partial Reconfiguration Interfaces on FPGAs: A Case Study. - Heng Tan; Ronald F. DeMara; Anuja Jayraj Thakkar; Abdel Ejnioui; Jason Sattler (ERSA, 2006)

Synthesis of Pipelined SRSL Circuits. - Rashad S. Oreifej; Abdelhalim Alsharqawi; Abdel Ejnioui (ISVLSI, 2006)

Clockless Pipelining for Coarse Grain Datapaths. - Abdelhalim Alsharqawi; Abdel Ejnioui (VLSI Design, 2006)

Hardware Acceleration of the Generalized Finite Automata Algorithm. - Abdel Ejnioui; Paul Bao (CDES, 2007)

Prototyping of a Two-Phase Micropipeline on FPGAs. - Abdel Ejnioui (ERSA, 2007)

Hardware Architectures for the Generalized Finite Automata Algorithm. - Abdel Ejnioui; Paul Bao (ICECS, 2007)

FPGA Prototyping of a Two-Phase Self-Oscillating Micropipeline. - Abdel Ejnioui (ISVLSI, 2007)

Role of the C language in current computing curricula part 1: survey analysis. - Alessio Gaspar; Naomi R. Boyer; Abdel Ejnioui (J. Comput. Sci. Coll., 2007)

Tiered Algorithm for Distributed Process Quiescence and Termination Detection. - Ronald F. DeMara; Yili Tseng; Abdel Ejnioui (IEEE Trans. Parallel Distributed Syst., 2007)

A parallel architecture for GFA modeling in video coding. - Abdel Ejnioui; Paul Bao (CIT, 2008)

A Parallel Array to Accelerate GFA Modeling in Video Coding. - Abdel Ejnioui; Paul Bao (ERSA, 2008)

Runtime Adaptation in Reconfigurable System-on-Chips. - Abdel Ejnioui (ICPP Workshops, 2009)

Evaluation of Information Security Controls in Organizations by Grey Relational Analysis. - Angel R. Otero; Abdel Ejnioui; Carlos E. Otero; Gurvirender Tejay 001 (Int. J. Dependable Trust. Inf. Syst., 2011)

A simulation-based fuzzy multi-attribute decision making for prioritizing software requirements. - Abdel Ejnioui; Carlos E. Otero; Luis Daniel Otero (RIIT, 2012)

Formalizing the design of embedded software using sequence diagrams and abstract state machines. - Abdel Ejnioui; Carlos E. Otero; Abrar A. Qureshi (RIIT, 2013)

Engineering graphic user interfaces with protected content. - Abdel Ejnioui; Carlos E. Otero; Abrar A. Qureshi (SysCon, 2013)

A support vector machine for terrain classification in on-demand deployments of wireless sensor networks. - Rana Haber; Adrian M. Peter; Carlos E. Otero; Ivica Kostanic; Abdel Ejnioui (SysCon, 2013)

System analysis methods in emergency systems. - Jeffrey A. McDougall; Luis Daniel Otero; Juan Avendano; Abdel Ejnioui (SysCon, 2013)

Prioritisation of software requirements using grey relational analysis. - Abdel Ejnioui; Carlos E. Otero; Luis Daniel Otero (Int. J. Comput. Appl. Technol., 2013)

A stochastic approach for evaluating quality of service in wireless cellular networks. - Abdel Ejnioui; Carlos E. Otero; Ivica Kostanic (Int. J. Wirel. Mob. Comput., 2013)

Adaptive Mitigation of Radiation-Induced Errors and TDDB in Reconfigurable Logic Fabrics. - Rawad N. Al-Haddad; Rashad S. Oreifej; Ramtin Zand; Abdel Ejnioui; Ronald F. DeMara (NATW, 2015)