Comparison of Self-Timed Ring and Inverter Ring Oscillators as entropy sources in FPGAs. - Abdelkarim Cherkaoui; Viktor Fischer; Alain Aubert; Laurent Fesquet (DATE, 2012)

A Self-Timed Ring Based True Random Number Generator. - Abdelkarim Cherkaoui; Viktor Fischer; Alain Aubert; Laurent Fesquet (ASYNC, 2013)

A Very High Speed True Random Number Generator with Entropy Assessment. - Abdelkarim Cherkaoui; Viktor Fischer; Laurent Fesquet; Alain Aubert (CHES, 2013)

Self-timed rings as low-phase noise programmable oscillators. - Laurent Fesquet; Abdelkarim Cherkaoui; Oussama Elissati (NEWCAS, 2014)

New paradigms for access control in constrained environments. - Abdelkarim Cherkaoui; Lilian Bossuet; Ludwig Seitz; Göran Selander; Ravishankar Borgaonkar (ReCoSoC, 2014)

Enhanced TERO-PUF Implementations and Characterization on FPGAs (Abstract Only). - Cédric Marchand 002; Lilian Bossuet; Abdelkarim Cherkaoui (FPGA, 2016)

Design and Characterization of the TERO-PUF on SRAM FPGAs. - Cédric Marchand 002; Lilian Bossuet; Abdelkarim Cherkaoui (ISVLSI, 2016)

New asynchronous protocols for enhancing area and throughput in bundled-data pipelines. - Jean Simatic; Abdelkarim Cherkaoui; Rodrigo Possamai Bastos; Laurent Fesquet (SBCCI, 2016)

Design, Evaluation, and Optimization of Physical Unclonable Functions Based on Transient Effect Ring Oscillators. - Abdelkarim Cherkaoui; Lilian Bossuet; Cédric Marchand 002 (IEEE Trans. Inf. Forensics Secur., 2016)

A Practical Framework for Specification, Verification, and Design of Self-Timed Pipelines. - Jean Simatic; Abdelkarim Cherkaoui; François Bertrand; Rodrigo Possamai Bastos; Laurent Fesquet (ASYNC, 2017)

CAR: On the highway towards de-synchronization. - François Bertrand; Abdelkarim Cherkaoui; Jean Simatic; Anthony Maure; Laurent Fesquet (ICECS, 2017)

Self-timed Ring based True Random Number Generator: Threat model and countermeasures. - Gregoire Gimenez; Abdelkarim Cherkaoui; Raphael Frisch; Laurent Fesquet (IVSW, 2017)

On-the-fly and sub-gate-delay resolution TDC based on self-timed ring: A proof of concept. - Assia El-Hadbi; Abdelkarim Cherkaoui; Oussama Elissati; Jean Simatic; Laurent Fesquet (NEWCAS, 2017)

Static Timing Analysis of Asynchronous Bundled-Data Circuits. - Gregoire Gimenez; Abdelkarim Cherkaoui; Guillaume Cogniard; Laurent Fesquet (ASYNC, 2018)

Subthreshold logic for low-area and energy efficient true random number generator. - Mathieu Coustans; Abdelkarim Cherkaoui; Laurent Fesquet; Christian Terrier; Stephanie Salgado; Thomas Eberhardt; Maher Kayal (COOL CHIPS, 2018)

Low Phase-Noise CMOS Quadrature Oscillator based on (N × 4)-stage Self-Timed Ring. - Oussama Elissati; Assia El-Hadbi; Abdelkarim Cherkaoui; Sébastien Rieubon; Laurent Fesquet (DCIS, 2018)

Implementation and Characterization of a Physical Unclonable Function for IoT: A Case Study With the TERO-PUF. - Cédric Marchand 002; Lilian Bossuet; Ugo Mureddu; Nathalie Bochard; Abdelkarim Cherkaoui; Viktor Fischer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

A Self-Timed Ring based PUF. - Grégoire Gimenez; Abdelkarim Cherkaoui; Laurent Fesquet (ASYNC, 2020)

An Energy Efficient Multi-Rail Architecture for Stochastic Computing: A Bayesian Sensor Fusion Case Study. - Jérémy Belot; Abdelkarim Cherkaoui; Raphaël Laurent; Laurent Fesquet (ICECS, 2021)

An Area- and Power-Efficient Stochastic Number Generator for Bayesian Sensor Fusion Circuits. - Jérémy Belot; Abdelkarim Cherkaoui; Raphaël Laurent; Laurent Fesquet (IEEE Des. Test, 2021)