A 328 μW 5 GHz voltage-controlled oscillator in 90 nm CMOS with high-quality thin-film post-processed inductor. - Dimitri Linten; Xiao Sun; Geert Carchon; Wutthinan Jeamsaksiri; Abdelkarim Mercha; Javier Ramos; Snezana Jenei; Lars Aspemyr; Andries J. Scholten; Piet Wambacq; Stefaan Decoutere; Stéphane Donnay; et al. (CICC, 2004)

Degradation of electrical performance and floating body effect in ultra thin gate oxide FD-SOI n-MOSFETs by 7.5-MeV proton irradiation. - Kiyoteru Hayama; Kenichiro Takakura; Hidenori Ohyama; Abdelkarim Mercha; Eddy Simoen; Cor Claeys; Joan Marc Rafí; Michael Kokkoris (Microelectron. Reliab., 2004)

Low-power low-noise highly ESD robust LNA, and VCO design using above-IC inductors. - Dimitri Linten; Xiao Sun; Steven Thijs; M. I. Natarajan; Abdelkarim Mercha; Geert Carchon; Piet Wambacq; Takeshi Nakaie; Stefaan Decoutere (CICC, 2005)

Technology and architecture for deep submicron RF CMOS technology. - Abdelkarim Mercha (SBCCI, 2005)

RFCV Test Structure Design for a Selected Frequency Range. - Wutthinan Jeamsaksiri; Abdelkarim Mercha; Javier Ramos; Stefaan Decoutere; Florence Cubaynes (IEICE Trans. Electron., 2005)

Low-power voltage-controlled oscillators in 90-nm CMOS using high-quality thin-film postprocessed inductors. - Dimitri Linten; Xiao Sun; Geert Carchon; Wutthinan Jeamsaksiri; Abdelkarim Mercha; Javier Ramos; Snezana Jenei; Piet Wambacq; Morin Dehan; Lars Aspemyr; Andries J. Scholten; Stefaan Decoutere; et al. (IEEE J. Solid State Circuits, 2005)

A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS. - Dimitri Linten; Steven Thijs; Mahadeva Iyer Natarajan; Piet Wambacq; Wutthinan Jeamsaksiri; Javier Ramos; Abdelkarim Mercha; Snezana Jenei; Stéphane Donnay; Stefaan Decoutere (IEEE J. Solid State Circuits, 2005)

Radiation source dependence of performance degradation in thin gate oxide fully-depleted SOI n-MOSFETs. - Kiyoteru Hayama; Kenichiro Takakura; Hidenori Ohyama; S. Kuboyama; S. Matsuda; Joan Marc Rafí; Abdelkarim Mercha; Eddy Simoen; Cor Claeys (Microelectron. Reliab., 2005)

Technologies for (sub-) 45nm Analog/RF CMOS - Circuit Design Opportunities and Challenges. - Stefaan Decoutere; Piet Wambacq; Vaidy Subramanian; Jonathan Borremans; Abdelkarim Mercha (CICC, 2006)

Impact on the back gate degradation in partially depleted SOI n-MOSFETs by 2-MeV electron irradiation. - Kiyoteru Hayama; Kenichiro Takakura; K. Shigaki; Hidenori Ohyama; Joan Marc Rafí; Abdelkarim Mercha; Eddy Simoen; Cor Claeys (Microelectron. Reliab., 2006)

Hot-carrier-induced degradation of drain current hysteresis and transients in thin gate oxide floating body partially depleted SOI nMOSFETs. - Joan Marc Rafí; Eddy Simoen; Kiyoteru Hayama; Abdelkarim Mercha; Francesca Campabadal; Hidenori Ohyama; Cor Claeys (Microelectron. Reliab., 2006)

An Accurate Scalable Compact Model for the Substrate Resistance of RF MOSFETs. - Bertrand Parvais; S. Hu; Morin Dehan; Abdelkarim Mercha; Stefaan Decoutere (CICC, 2007)

Analog design challenges and trade-offs using emerging materials and devices. - Michael Fulde; Abdelkarim Mercha; Cedric Gustin; Bertrand Parvais; Vaidyanathan Subramanian; Klaus von Arnim; Florian Bauer; Klaus Schruefer; Doris Schmitt-Landsiedel; Gerhard Knoblinger (ESSCIRC, 2007)

FinFET technology for analog and RF circuits. - Bertrand Parvais; Vaidyanathan Subramanian; Abdelkarim Mercha; Morin Dehan; Piet Wambacq; Willy Sansen; Guido Groeseneken; Stefaan Decoutere (ICECS, 2007)

High-temperature performance of state-of-the-art triple-gate transistors. - Kerem Akarvardar; Abdelkarim Mercha; Eddy Simoen; Vaidyanathan Subramanian; Cor Claeys; Pierre Gentil; Sorin Cristoloveanu (Microelectron. Reliab., 2007)

The Potential of FinFETs for Analog and RF Circuit Applications. - Piet Wambacq; Bob Verbruggen; Karen Scheir; Jonathan Borremans; Morin Dehan; Dimitri Linten; Vincent De Heyn; Geert Van der Plas; Abdelkarim Mercha; Bertrand Parvais; Cedric Gustin; Vaidyanathan Subramanian; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies. - Piet Wambacq; Abdelkarim Mercha; Karen Scheir; Bob Verbruggen; Jonathan Borremans; Vincent De Heyn; Steven Thijs; Dimitri Linten; Geert Van der Plas; Bertrand Parvais; Morin Dehan; Stefaan Decoutere; et al. (ISSCC, 2008)

3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV). - Jan Van Olmen; Jan Coenen; Wim Dehaene; Kristin De Meyer; Cedric Huyghebaert; Anne Jourdain; Guruprasad Katti; Abdelkarim Mercha; Michal Rakowski; Michele Stucchi; Youssef Travaly; Eric Beyne; et al. (3DIC, 2009)

Low-cost feedback-enabled LNAs in 45nm CMOS. - Jonathan Borremans; Steven Thijs; Morin Dehan; Abdelkarim Mercha; Piet Wambacq (ESSCIRC, 2009)

Migrating from planar to FinFET for further CMOS scaling: SOI or bulk? - Thomas Chiarella; Liesbeth Witters; Abdelkarim Mercha; Christoph Kerner; Rok Dittrich; Michal Rakowski; Claude Ortolland; Lars-Åke Ragnarsson; Bertrand Parvais; An De Keersgieter; Stefan Kubicek; Augusto Redolfi; et al. (ESSCIRC, 2009)

FinFET RF receiver building blocks operating above 10 GHz. - Domagoj Siprak; Piet Wambacq; Bertrand Parvais; Abdelkarim Mercha; Michael Fulde; Jesenka Veledar Kruger; Morin Dehan; Stefaan Decoutere (ESSCIRC, 2009)

Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions. - Geert Van der Plas; Steven Thijs; Dimitri Linten; Guruprasad Katti; Paresh Limaye; Abdelkarim Mercha; Michele Stucchi; Herman Oprins; Bart Vandevelde; Nikolaos Minas; Miro Cupac; Morin Dehan; et al. (CICC, 2010)

3D integration: Circuit design, test, and reliability challenges. - Nikolaos Minas; Ingrid De Wolf; Erik Jan Marinissen; Michele Stucchi; Herman Oprins; Abdelkarim Mercha; Geert Van der Plas; Dimitrios Velenis; Pol Marchal (IOLTS, 2010)

45-nm Planar bulk-CMOS 23-GHz LNAs with high-Q above-IC inductors. - Wen-Chieh Wang; Zue-Der Huang; Geert Carchon; Abdelkarim Mercha; Stefaan Decoutere; Walter De Raedt; Chung-Yu Wu (ISCAS, 2010)

Design issues and considerations for low-cost 3D TSV IC technology. - Geert Van der Plas; Paresh Limaye; Abdelkarim Mercha; Herman Oprins; Cristina Torregiani; Steven Thijs; Dimitri Linten; Michele Stucchi; Guruprasad Katti; Dimitrios Velenis; Domae Shinichi; Vladimir Cherman; et al. (ISSCC, 2010)

Identifying the Bottlenecks to the RF Performance of FinFETs. - Vaidyanathan Subramanian; Abdelkarim Mercha; Bertrand Parvais; Morin Dehan; Guido Groeseneken; Willy M. C. Sansen; Stefaan Decoutere (VLSI Design, 2010)

Analysis of microbump induced stress effects in 3D stacked IC technologies. - Andrej Ivankovic; Geert Van der Plas; V. Moroz; M. Choi; Vladimir Cherman; Abdelkarim Mercha; Paul Marchal; Marcel Gonzalez; Geert Eneman; Wenqi Zhang; Thibault Buisson; Mikael Detalle; et al. (3DIC, 2011)

An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations. - Geert Eneman; J. Cho; V. Moroz; Dragomir Milojevic; M. Choi; Kristin De Meyer; Abdelkarim Mercha; Eric Beyne; Thomas Hoffmann 001; Geert Van der Plas (DATE, 2011)

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. - Geert Van der Plas; Paresh Limaye; Igor Loi; Abdelkarim Mercha; Herman Oprins; Cristina Torregiani; Steven Thijs; Dimitri Linten; Michele Stucchi; Guruprasad Katti; Dimitrios Velenis; Vladimir Cherman; et al. (IEEE J. Solid State Circuits, 2011)

3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps. - Wei Guo; Geert Van der Plas; Andrej Ivankovic; Geert Eneman; Vladimir Cherman; Bart De Wachter; Abdelkarim Mercha; Mario Gonzalez; Yann Civale; Augusto Redolfi; Thibault Buisson; A. Jourdan; et al. (ICICDT, 2012)

TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes. - Arindam Mallik; Paul Zuber; Tsung-Te Liu; Bharani Chava; Bhavana Ballal; Pablo Royer Del Bario; Rogier Baert; Kris Croes; Julien Ryckaert; Mustafa Badaroglu; Abdelkarim Mercha; Diederik Verkest (DAC, 2013)

STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process. - Doyoung Jang; Marie Garcia Bardon; Dmitry Yakimets; Kenichi Miyaguchi; An De Keersgieter; Thomas Chiarella; Romain Ritzenthaler; Morin Dehan; Abdelkarim Mercha (ESSDERC, 2013)

Design Technology co-optimization for N10. - Julien Ryckaert; Praveen Raghavan; Rogier Baert; Marie Garcia Bardon; Mircea Dusa; Arindam Mallik; Sushil Sakhare; Boris Vandewalle; Piet Wambacq; Bharani Chava; Kris Croes; Morin Dehan; et al. (CICC, 2014)

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies. - Trong Huynh Bao; Dmitry Yakimets; Julien Ryckaert; Ivan Ciofi; Rogier Baert; Anabela Veloso; Jürgen Bömmels; Nadine Collaert; Philippe Roussel; S. Demuynck; Praveen Raghavan; Abdelkarim Mercha; et al. (ESSDERC, 2014)

A digital intensive circuit for low-frequency noise monitoring in 28nm CMOS. - Bertrand Parvais; Piet Wambacq; Abdelkarim Mercha; Diederik Verkest; Aaron Thean; Ken Sawada; Kazuki Nomoto; Tetsuya Oishi; Hiroaki Ammo (A-SSCC, 2015)

Holisitic device exploration for 7nm node. - Praveen Raghavan; Marie Garcia Bardon; Doyoung Jang; P. Schuddinck; Dmitry Yakimets; Julien Ryckaert; Abdelkarim Mercha; Naoto Horiguchi; Nadine Collaert; Anda Mocuta; Dan Mocuta; Zsolt Tokei; et al. (CICC, 2015)

Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM. - Trong Huynh Bao; Sushil Sakhare; Julien Ryckaert; Dmitry Yakimets; Abdelkarim Mercha; Diederik Verkest; Aaron Voon-Yew Thean; Piet Wambacq (ICICDT, 2015)

Dimensioning for power and performance under 10nm: The limits of FinFETs scaling. - Marie Garcia Bardon; P. Schuddinck; Praveen Raghavan; Doyoung Jang; Dmitry Yakimets; Abdelkarim Mercha; Diederik Verkest; Aaron Thean (ICICDT, 2015)

Impact of device and interconnect process variability on clock distribution. - Nathalie Fievet; Praveen Raghavan; Rogier Baert; Frédéric Robert; Abdelkarim Mercha; Diederik Verkest; Aaron Thean (ICICDT, 2015)

Modeling FinFET metal gate stack resistance for 14nm node and beyond. - Kenichi Miyaguchi; Bertrand Parvais; Lars-Åke Ragnarsson; Piet Wambacq; Praveen Raghavan; Abdelkarim Mercha; Anda Mocuta; Diederik Verkest; Aaron Thean (ICICDT, 2015)

Impact of fin shape variability on device performance towards 10nm node. - Kazuyuki Tomida; Keizo Hiraga; Morin Dehan; Geert Hellings; Doyoung Jang; Kenichi Miyaguchi; Thomas Chiarella; Minsoo Kim; Anda Mocuta; Naoto Horiguchi; Abdelkarim Mercha; Diederik Verkest; et al. (ICICDT, 2015)

Lateral NWFET optimization for beyond 7nm nodes. - Dmitry Yakimets; Doyoung Jang; Praveen Raghavan; Geert Eneman; Hans Mertens; P. Schuddinck; Arindam Mallik; Marie Garcia Bardon; Nadine Collaert; Abdelkarim Mercha; Diederik Verkest; Aaron Thean; et al. (ICICDT, 2015)

Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond. - Trong Huynh Bao; Julien Ryckaert; Zsolt Tokei; Abdelkarim Mercha; Diederik Verkest; Aaron Voon-Yew Thean; Piet Wambacq (IEEE Trans. Very Large Scale Integr. Syst., 2017)