Testing the Logic Cells and Interconnect Resources for FPGAs. - Abderrahim Doumar; Hideo Ito (Asian Test Symposium, 1999)

Defect and Fault Tolerance FPGAs by Shifting the Configuration Data. - Abderrahim Doumar; Satoshi Kaneko; Hideo Ito (DFT, 1999)

Design of an automatic testing for FPGAs. - Abderrahim Doumar; Toshiaki Ohmameuda; Hideo Ito (ETW, 1999)

An Automatic Testing and Diagnosis for FPGAs. - Abderrahim Doumar; Hideo Ito (PRDC, 1999)

Testing approach within FPGA-based fault tolerant systems. - Abderrahim Doumar; Hideo Ito (Asian Test Symposium, 2000)

Design of Switching Blocks Tolerating Defects/Faults in FPGA Interconnection Resources. - Abderrahim Doumar; Hideo Ito (DFT, 2000)

Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey. - Abderrahim Doumar; Hideo Ito (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift. - Kentaroh Katoh; Abderrahim Doumar; Hideo Ito (IOLTS, 2005)

Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability. - Abderrahim Doumar; Kentaroh Katoh; Hideo Ito (DFT, 2007)

A novel SRAM-based FPGA architecture for defect and fault tolerance of configurable logic blocks. - Farid Lahrach; Abderrazek Abdaoui; Abderrahim Doumar; Eric Châtelet (DDECS, 2010)

Master-Slave TMR Inspired Technique for Fault Tolerance of SRAM-Based FPGA. - Farid Lahrach; Abderrahim Doumar; Eric Châtelet; Abderrazek Abdaoui (ISVLSI, 2010)

Fault tolerance of SRAM-based FPGA via configuration frames. - Farid Lahrach; Abderrahim Doumar; Eric Châtelet (DDECS, 2011)

Fault Tolerance of Multiple Logic Faults in SRAM-Based FPGA Systems. - Farid Lahrach; Abderrahim Doumar; Eric Châtelet (DSD, 2011)

Video acquisition between USB 2.0 CMOS camera and embedded FPGA system. - Abderrazak Abdaoui; K. Gurram; M. Singh; A. Errandani; Eric Châtelet; Abderrahim Doumar; Tarek M. El-Fouly (ICSPCS, 2011)