Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level. - Yuvraj Singh Dhillon; Abdulkadir Utku Diril; Abhijit Chatterjee; Hsien-Hsin S. Lee (ICCAD, 2003)

An O(N)Supply Voltage Assignment Algorithm for Low-Energy Serially Connected CMOS Modules and a Heuristic Extension to Acyclic Data Flow Graphs. - Abdulkadir Utku Diril; Yuvraj Singh Dhillon; Kyu-won Choi; Abhijit Chatterjee (ISVLSI, 2003)

Sizing CMOS Circuits for Increased Transient Error Tolerance. - Yuvraj Singh Dhillon; Abdulkadir Utku Diril; Abhijit Chatterjee; Adit D. Singh (IOLTS, 2004)

Low-power dual Vth pseudo dual Vdd domino circuits. - Yuvraj Singh Dhillon; Abdulkadir Utku Diril; Abhijit Chatterjee; Adit D. Singh (SBCCI, 2004)

Low-power domino circuits using NMOS pull-up on off-critical paths. - Abdulkadir Utku Diril; Yuvraj Singh Dhillon; Abhijit Chatterjee; Adit D. Singh (ASP-DAC, 2005)

Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits. - Yuvraj Singh Dhillon; Abdulkadir Utku Diril; Abhijit Chatterjee (DATE, 2005)

Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits. - Yuvraj Singh Dhillon; Abdulkadir Utku Diril; Abhijit Chatterjee; Cecilia Metra (IOLTS, 2005)

Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance. - Abdulkadir Utku Diril; Yuvraj Singh Dhillon; Abhijit Chatterjee; Adit D. Singh (VTS, 2005)

Pseudo Dual Supply Voltage Domino Logic Design. - Abdulkadir Utku Diril; Yuvraj Singh Dhillon; Abhijit Chatterjee; Adit D. Singh (J. Low Power Electron., 2005)

Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages. - Abdulkadir Utku Diril; Yuvraj Singh Dhillon; Abhijit Chatterjee; Adit D. Singh (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Circuit Level Techniques for Power and Reliability Optimization of CMOS Logic. - Abdulkadir Utku Diril (2005)

Adaptive Design for Performance-Optimized Robustness. - Ramyanshu Datta; Jacob A. Abraham; Abdulkadir Utku Diril; Abhijit Chatterjee; Kevin J. Nowka (DFT, 2006)

Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance. - Yuvraj Singh Dhillon; Abdulkadir Utku Diril; Abhijit Chatterjee; Adit D. Singh (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations. - Maryam Ashouei; Muhammad Mudassar Nisar; Abhijit Chatterjee; Adit D. Singh; Abdulkadir Utku Diril (VLSI Design, 2007)

Delay-Assignment-Variation Based Optimization of Digital CMOS Circuits for Low Power Consumption. - Yuvraj Singh Dhillon; Abdulkadir Utku Diril; Abhijit Chatterjee (J. Low Power Electron., 2007)

Performance-Optimized Design for Parametric Reliability. - Ramyanshu Datta; Jacob A. Abraham; Abdulkadir Utku Diril; Abhijit Chatterjee; Kevin J. Nowka (J. Electron. Test., 2008)