Instruction Profiling Based Fetch Throttling for Wasted Dynamic Power Reduction. - Abdullah A. Owahid; Eugene B. John (SBAC-PAD, 2019)

Wasted dynamic power and correlation to instruction set architecture for CPU throttling. - Abdullah A. Owahid; Eugene B. John (J. Supercomput., 2019)

All-Digital Closed-Loop Unified Retention/Wake-Up Clamp in a 10nm 4-Core x86 IP. - Charles Augustine; A. Afzal; U. Misgar; Abdullah A. Owahid; A. Raman; K. Subramanian; Feroze Merchant; James W. Tschanz; Muhammad M. Khellah (VLSI Circuits, 2021)

Instruction Profiling Based Predictive Throttling for Power and Performance. - Abdullah A. Owahid; Eugene B. John (IEEE Trans. Computers, 2023)