An Efficient Design Approach for Implementation of 2 Bit Ternary Flash ADC Using Optimized Complementary TFET Devices. - Sanjay Vidhyadharan; Ramakant Ramakant; Abhay S. Vidhyadharan; A. Krishna Shyam; Mohit P. Hirpara; Surya Shankar Dan (VLSID, 2019)

Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC. - Sanjay Vidhyadharan; Surya Shankar Dan; Abhay S. Vidhyadharan; Ramakant Yadav; Simhadri Hariprasad (Integr., 2020)

CNFET-Based Ultra-Low-Power Dual-VDD Ternary Half Adder. - Abhay S. Vidhyadharan; Kasthuri Bha; Sanjay Vidhyadharan (Circuits Syst. Signal Process., 2021)

An ultra-low-power CNFET based dual VDD ternary dynamic Half Adder. - Abhay S. Vidhyadharan; Sanjay Vidhyadharan (Microelectron. J., 2021)

A novel ultra-low-power CNTFET and 45 nm CMOS based ternary SRAM. - Abhay S. Vidhyadharan; Sanjay Vidhyadharan (Microelectron. J., 2021)

High-Speed and Area-Efficient CMOS and CNFET-Based Level-Shifters. - Abhay S. Vidhyadharan; Aiswarya Satheesh; Kilari Pragnaa; Sanjay Vidhyadharan (Circuits Syst. Signal Process., 2022)

CNFET Based Ultra-Low-Power Schmitt Trigger SRAM for Internet of Things (IoT) Applications. - Abhay S. Vidhyadharan; Sanjay Vidhyadharan (Wirel. Pers. Commun., 2022)