Test vector decompression via cyclical scan chains and its application to testing core-based designs. - Abhijit Jas; Nur A. Touba (ITC, 1998)

An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets. - Abhijit Jas; Kartik Mohanram; Nur A. Touba (Asian Test Symposium, 1999)

Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip. - Abhijit Jas; Nur A. Touba (ICCD, 1999)

Configuration self-test in FPGA-based reconfigurable systems. - W. Quddus; Abhijit Jas; Nur A. Touba (ISCAS (1), 1999)

Scan Vector Compression/Decompression Using Statistical Coding. - Abhijit Jas; Jayabrata Ghosh-Dastidar; Nur A. Touba (VTS, 1999)

Virtual Scan Chains: A Means for Reducing Scan Length in Cores. - Abhijit Jas; Bahram Pouya; Nur A. Touba (VTS, 2000)

Test vector encoding using partial LFSR reseeding. - C. V. Krishna; Abhijit Jas; Nur A. Touba (ITC, 2001)

Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning Scheme. - Abhijit Jas; C. V. Krishna; Nur A. Touba (VTS, 2001)

Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor. - Abhijit Jas; Nur A. Touba (J. Electron. Test., 2002)

An efficient test vector compression scheme using selective Huffman coding. - Abhijit Jas; Jayabrata Ghosh-Dastidar; Mom-Eng Ng; Nur A. Touba (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Achieving high encoding efficiency with partial dynamic LFSR reseeding. - C. V. Krishna; Abhijit Jas; Nur A. Touba (ACM Trans. Design Autom. Electr. Syst., 2004)

Weighted pseudorandom hybrid BIST. - Abhijit Jas; C. V. Krishna; Nur A. Touba (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Test data compression technique for embedded cores using virtual scan chains. - Abhijit Jas; Bahram Pouya; Nur A. Touba (IEEE Trans. Very Large Scale Integr. Syst., 2004)

An Approach to Minimizing Functional Constraints. - Abhijit Jas; Yi-Shing Chang; Sreejit Chakravarty (DFT, 2006)

The Region-Exhaustive Fault Model. - Abhijit Jas; Suriyaprakash Natarajan; Srinivas Patil (ATS, 2007)

Analysis of Specified Bit Handling Capability of Combinational Expander Networks. - Abhijit Jas; Srinivas Patil (DFT, 2007)

A low-cost concurrent error detection technique for processor control logic. - Ramtilak Vemu; Abhijit Jas; Jacob A. Abraham; Srinivas Patil; Rajesh Galivanche (DATE, 2008)

Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller. - Michail Maniatakos; Naghmeh Karimi; Yiorgos Makris; Abhijit Jas; Chandra Tirumurti (DFT, 2008)

Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic. - Cecilia Metra; Daniele Rossi 001; Martin Omaña 001; Abhijit Jas; Rajesh Galivanche (ETS, 2008)

Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes. - Avijit Dutta; Abhijit Jas (ISQED, 2008)

On the Correlation between Controller Faults and Instruction-Level Errors in Modern Microprocessors. - Naghmeh Karimi; Michail Maniatakos; Abhijit Jas; Yiorgos Makris (ITC, 2008)

A Methodology for Handling Complex Functional Constraints for Large Industrial Designs. - Abhijit Jas; Yi-Shing Chang; Sreejit Chakravarty (J. Electron. Test., 2008)

Impact analysis of performance faults in modern microprocessors. - Naghmeh Karimi; Michail Maniatakos; Chandra Tirumurti; Abhijit Jas; Yiorgos Makris (ICCD, 2009)

RT-Level Deviation-Based Grading of Functional Test Sequences. - Hongxia Fang; Krishnendu Chakrabarty; Abhijit Jas; Srinivas Patil; Chandra Tirumurti (VTS, 2009)

Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller. - Michail Maniatakos; Naghmeh Karimi; Chandra Tirumurti; Abhijit Jas; Yiorgos Makris (VTS, 2009)

FPGA-based hardware acceleration for Boolean satisfiability. - Kanupriya Gulati; Suganth Paul; Sunil P. Khatri; Srinivas Patil; Abhijit Jas (ACM Trans. Design Autom. Electr. Syst., 2009)

Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors. - Daniele Rossi 001; Martin Omaña 001; Gianluca Berghella; Cecilia Metra; Abhijit Jas; Chandra Tirumurti; Rajesh Galivanche (Conf. Computing Frontiers, 2010)

Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering. - Debasish Das; Kip Killpack; Chandramouli V. Kashyap; Abhijit Jas; Hai Zhou 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

AVF Analysis Acceleration via Hierarchical Fault Pruning. - Michail Maniatakos; Chandra Tirumurti; Abhijit Jas; Yiorgos Makris (ETS, 2011)

Workload-Cognizant Concurrent Error Detection in the Scheduler of a Modern Microprocessor. - Naghmeh Karimi; Michail Maniatakos; Abhijit Jas; Chandra Tirumurti; Yiorgos Makris (IEEE Trans. Computers, 2011)

Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller. - Michail Maniatakos; Naghmeh Karimi; Chandra Tirumurti; Abhijit Jas; Yiorgos Makris (IEEE Trans. Computers, 2011)

Functional Test-Sequence Grading at Register-Transfer Level. - Hongxia Fang; Krishnendu Chakrabarty; Abhijit Jas; Srinivas Patil; Chandra Tirumurti (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder. - Daniele Rossi 001; Martin Omaña 001; G. Garrammone; Cecilia Metra; Abhijit Jas; Rajesh Galivanche (J. Electron. Test., 2013)