A matrix transform imager allowing high-fill factor. - Paul E. Hasler; Abhishek Bandyopadhyay; Paul D. Smith (ISCAS (3), 2002)

A fully programmable CMOS block matrix transform imager architecture. - Abhishek Bandyopadhyay; Paul E. Hasler (CICC, 2003)

High Fill-Factor Imagers for Neuromorphic Processing Enabled by Floating-Gate Circuits. - Paul E. Hasler; Abhishek Bandyopadhyay; David V. Anderson (EURASIP J. Adv. Signal Process., 2003)

A 531 nW/MHz, 128×32 current-mode programmable analog vector-matrix multiplier with over two decades of linearity. - Ravi Chawla; Abhishek Bandyopadhyay; Venkatesh Srinivasan; Paul E. Hasler (CICC, 2004)

Matrix Transform Imager Architecture for On-Chip Low-Power Image Processing. - Abhishek Bandyopadhyay (2004)

Image processing system using a programmable transform imager. - Jungwon Lee; Abhishek Bandyopadhyay; I. Faik Baskaya; Ryan W. Robucci; Paul E. Hasler (ICASSP (5), 2005)

A 80µW/frame 104×128 CMOS imager front end for JPEG compression. - Abhishek Bandyopadhyay; Jungwon Lee; Ryan W. Robucci; Paul E. Hasler (ISCAS (5), 2005)

Programming analog computational memory elements to 0.2% accuracy over 3.5 decades using a predictive method. - Abhishek Bandyopadhyay; Guillermo J. Serrano; Paul E. Hasler (ISCAS (3), 2005)

MATIA: a programmable 80 WμW/frame CMOS block matrix transform imager architecture. - Abhishek Bandyopadhyay; Jungwon Lee; Ryan W. Robucci; Paul E. Hasler (IEEE J. Solid State Circuits, 2006)

Adaptive Algorithm Using Hot-Electron Injection for Programming Analog Computational Memory Elements Within 0.2% of Accuracy Over 3.5 Decades. - Abhishek Bandyopadhyay; Guillermo J. Serrano; Paul E. Hasler (IEEE J. Solid State Circuits, 2006)

A 108dB SNR 1.1mW Oversampling Audio DAC with a Three-Level DEM Technique. - Khiem Nguyen; Abhishek Bandyopadhyay; Bob Adams 001; Karl Sweetland; Paul Baginski (ISSCC, 2008)

A 108 dB SNR, 1.1 mW Oversampling Audio DAC With A Three-level DEM Technique. - Khiem Nguyen; Abhishek Bandyopadhyay; Bob Adams 001; Karl Sweetland; Paul Baginski (IEEE J. Solid State Circuits, 2008)

A 120dB-SNR 100dB-THD+N 21.5mW/channel multibit CT ΔΣ DAC. - Abhishek Bandyopadhyay; Michael Determan; Sejun Kim; Khiem Nguyen (ISSCC, 2011)

Dynamic survivable traffic grooming with effective load balancing in WDM all-optical mesh networks. - Abhishek Bandyopadhyay; Mohtasham Raghib; Uma Bhattacharya; Monish Chatterjee (ICACCI, 2014)

A 97.3 dB SNR, 600 kHz BW, 31mW multibit continuous time ΔΣ ADC. - Abhishek Bandyopadhyay; Robert Adams 001; Khiem Nguyen; Paul Baginski; David Lamb; Thomas Tansley (VLSIC, 2014)

Improved algorithms for dynamic routing and wavelength assignment in WDM all-optical mesh networks. - Abhishek Bandyopadhyay; Ajanta Sarkar; Uma Bhattacharya; Monish Chatterjee (WOCN, 2014)

Session 18 - Data converter techniques. - John A. McNeill; Abhishek Bandyopadhyay (CICC, 2015)

An offline scheme for reducing cost of protection in all-optical WDM mesh networks with fast recovery. - Vishal Dey; Abhishek Bandyopadhyay; Uma Bhattacharya; Monish Chatterjee (Int. J. Parallel Emergent Distributed Syst., 2019)

31.1 An 82mW ΔΣ - Based Filter-Less Class-D Headphone Amplifier with -93dB THD+N, 113dB SNR and 93% Efficiency. - Atsushi Matamura; Naoaki Nishimura; Preston Birdsong; Abhishek Bandyopadhyay; Adam Spirer; Mariana T. Markova; Shaolong Liu (ISSCC, 2021)

An 82-mW ΔΣ-Based Filter-Less Class-D Headphone Amplifier With -93-dB THD+N, 113-dB SNR, and 93% Efficiency. - Atsushi Matamura; Naoaki Nishimura; Preston Birdsong; Abhishek Bandyopadhyay; Adam Spirer; Mariana T. Markova; Shaolong Liu (IEEE J. Solid State Circuits, 2021)

Common-mode Stable Multilevel Output Stage with EMI Reduction Feedback Loop for Class-D audio Amplifier. - Naoaki Nishimura; Atsushi Matamura; Preston Birdsong; Shaolong Liu; Abhishek Bandyopadhyay; Mariana T. Markova; Rajeev Morajkar (VLSI Technology and Circuits, 2022)