Abhishek Chakraborty

Orcid: 0000-0003-2948-6326

Affiliations:
  • University of Maryland, USA
  • Indian Institute of Technology Kharagpur, India (former)


According to our database1, Abhishek Chakraborty authored at least 25 papers between 2014 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2022
DynaMarks: Defending Against Deep Learning Model Extraction Using Dynamic Watermarking.
CoRR, 2022

2021
Design Techniques for Enhancing Hardware-Oriented Security Using Obfuscation.
PhD thesis, 2021

Evaluating the Security of Delay-Locked Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Robust and Attack Resilient Logic Locking with a High Application-Level Impact.
ACM J. Emerg. Technol. Comput. Syst., 2021

2020
Keynote: A Disquisition on Logic Locking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Strong Anti-SAT: Secure and Effective Logic Locking.
IACR Cryptol. ePrint Arch., 2020

A Survey on Neural Trojans.
IACR Cryptol. ePrint Arch., 2020

Hardware-Assisted Intellectual Property Protection of Deep Learning Models.
IACR Cryptol. ePrint Arch., 2020

2019
Hardware-Software Co-Design Based Obfuscation of Hardware Accelerators.
IACR Cryptol. ePrint Arch., 2019

2018
TimingSAT: timing profile embedded SAT attack.
Proceedings of the International Conference on Computer-Aided Design, 2018

GPU obfuscation: attack and defense strategies.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Fault Space Transformation: A Generic Approach to Counter Differential Fault Analysis and Differential Fault Intensity Analysis on AES-Like Block Ciphers.
IEEE Trans. Inf. Forensics Secur., 2017

A Combined Power and Fault Analysis Attack on Protected Grain Family of Stream Ciphers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Fault Tolerant Infective Countermeasure for AES.
J. Hardw. Syst. Secur., 2017

Correlation Power Analysis Attack against STT-MRAM Based Cyptosystems.
IACR Cryptol. ePrint Arch., 2017

Template Attack Based Deobfuscation of Integrated Circuits.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

2016
Template attack on SPA and FA resistant implementation of Montgomery ladder.
IET Inf. Secur., 2016

A Practical Template Attack on MICKEY-128 2.0 Using PSO Generated IVs and LS-SVM.
IACR Cryptol. ePrint Arch., 2016

2015
Using State Space Encoding To Counter Biased Fault Attacks on AES Countermeasures.
IACR Cryptol. ePrint Arch., 2015

Combined Side-Channel and Fault Analysis Attack on Protected Grain Family of Stream Ciphers.
IACR Cryptol. ePrint Arch., 2015

A practical DPA on Grain v1 using LS-SVM.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

Improved practical differential fault analysis of grain-128.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A Biased Fault Attack on the Time Redundancy Countermeasure for AES.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2015

2014
Multi-Bit Differential Fault Analysis of Grain-128 with Very Weak Assumptions.
IACR Cryptol. ePrint Arch., 2014

Fibonacci LFSR vs. Galois LFSR: Which is More Vulnerable to Power Attacks?
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2014


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