Abhishek Jain

According to our database, Abhishek Jain authored at least 14 papers between 2008 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Radiation Tolerant Multi-Bit Flip-Flop System With Embedded Timing Pre-Error Sensing.

Abhishek Jain, Andrea Mario Veggetti, Dennis Crippa, Antonio Benfante, Simone Gerardin, Marta Bagatin

IEEE J. Solid State Circuits, 2022

2020

Single Phase Clock Based Radiation Tolerant D Flip-flop Circuit.

Abhishek Jain, Andrea Veggetti, Dennis Crippa, Antonio Benfante, Simone Gerardin, Marta Bagatin

Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

2017

Cognitive approach to support dynamic aging compensation.

Souhir Mhira, Vincent Huard, Ahmed Benhassain, Florian Cacho, David Meyer, Sylvie Naudet, Abhishek Jain, C. R. Parthasarathy, Alain Bravaix

Proceedings of the IEEE International Test Conference, 2017

Dynamic aging compensation and Safety measures in Automotive environment.

Souhir Mhira, Vincent Huard, Ahmed Benhassain, Florian Cacho, Sylvie Naudet, Abhishek Jain, C. R. Parthasarathy, Alain Bravaix

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

2016

Unified and Modular Modeling and Functional Verification Framework of Real-Time Image Signal Processors.

Abhishek Jain, Richa Gupta

VLSI Design, 2016

Activity profiling: Review of different solutions to develop reliable and performant design.

Florian Cacho, Ahmed Benhassain, Souhir Mhira, Ajith Sivadasan, Vincent Huard, P. Cathelin, Vincent Knopik, Abhishek Jain, C. R. Parthasarathy, Lorena Anghel

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

2015

Scaling the UVM_REG Model towards Automation and Simplicity of Use.

Abhishek Jain, Richa Gupta

Proceedings of the 28th International Conference on VLSI Design, 2015

Timing in-situ monitors: Implementation strategy and applications results.

Ahmed Benhassain, Florian Cacho, Vincent Huard, M. Saliva, Lorena Anghel, C. R. Parthasarathy, Abhishek Jain, Fabien Giner

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

Early Development of UVM based Verification Environment of Image Signal Processing Designs using TLM Reference Model of RTL.

Abhishek Jain, Hima Gupta, Sandeep Jana, Krishna Kumar

CoRR, 2014

Accelerating SystemVerilog UVM Based VIP to Improve Methodology for Verification of Image Signal Processing Designs Using HW Emulator.

Abhishek Jain, Piyush Kumar Gupta, Hima Gupta, Sachish Dhar

CoRR, 2014

2013

Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for Efficient Verification of Image Signal Processing IPs/SoCs

Abhishek Jain, Giuseppe Bonanno, Hima Gupta, Ajay Goyal

CoRR, 2013

2012

On-chip delay measurement circuit.

Abhishek Jain, Andrea Veggetti, Dennis Crippa, Pierluigi Rolandi

Proceedings of the 17th IEEE European Test Symposium, 2012

2010

An On-Chip Flip-Flop Characterization Circuit.

Abhishek Jain, Andrea Veggetti, Dennis Crippa, Pierluigi Rolandi

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

2008

A novel approach to video matting using automated scribbling by motion analysis.

Abhishek Jain, Madhur Agrawal, Abhinav Gupta, Vineet Khandelwal

Proceedings of the IEEE International Conference on Virtual Environments, 2008