A novel approach to video matting using automated scribbling by motion analysis. - Abhishek Jain 003; Madhur Agrawal; Abhinav Gupta 006; Vineet Khandelwal (VECIMS, 2008)

An On-Chip Flip-Flop Characterization Circuit. - Abhishek Jain 003; Andrea Veggetti 001; Dennis Crippa; Pierluigi Rolandi (PATMOS, 2010)

On-chip delay measurement circuit. - Abhishek Jain 003; Andrea Veggetti 001; Dennis Crippa; Pierluigi Rolandi (ETS, 2012)

Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for Efficient Verification of Image Signal Processing IPs/SoCs - Abhishek Jain 003; Giuseppe Bonanno; Hima Gupta; Ajay Goyal (CoRR, 2013)

Accelerating SystemVerilog UVM Based VIP to Improve Methodology for Verification of Image Signal Processing Designs Using HW Emulator. - Abhishek Jain 003; Piyush Kumar Gupta; Hima Gupta; Sachish Dhar (CoRR, 2014)

Early Development of UVM based Verification Environment of Image Signal Processing Designs using TLM Reference Model of RTL. - Abhishek Jain 003; Hima Gupta; Sandeep Jana; Krishna Kumar (CoRR, 2014)

Timing in-situ monitors: Implementation strategy and applications results. - Ahmed Benhassain; Florian Cacho; Vincent Huard; M. Saliva; Lorena Anghel; C. R. Parthasarathy; Abhishek Jain 003; Fabien Giner (CICC, 2015)

Scaling the UVM_REG Model towards Automation and Simplicity of Use. - Abhishek Jain 003; Richa Gupta (VLSID, 2015)

Activity profiling: Review of different solutions to develop reliable and performant design. - Florian Cacho; Ahmed Benhassain; Souhir Mhira; Ajith Sivadasan; Vincent Huard; P. Cathelin; Vincent Knopik; Abhishek Jain 003; C. R. Parthasarathy; Lorena Anghel (IOLTS, 2016)

Unified and Modular Modeling and Functional Verification Framework of Real-Time Image Signal Processors. - Abhishek Jain 003; Richa Gupta (VLSI Design, 2016)

Dynamic aging compensation and Safety measures in Automotive environment. - Souhir Mhira; Vincent Huard; Ahmed Benhassain; Florian Cacho; Sylvie Naudet; Abhishek Jain 003; C. R. Parthasarathy; Alain Bravaix (IOLTS, 2017)

Cognitive approach to support dynamic aging compensation. - Souhir Mhira; Vincent Huard; Ahmed Benhassain; Florian Cacho; David Meyer; Sylvie Naudet; Abhishek Jain 003; C. R. Parthasarathy; Alain Bravaix (ITC, 2017)

Single Phase Clock Based Radiation Tolerant D Flip-flop Circuit. - Abhishek Jain 003; Andrea Veggetti 001; Dennis Crippa; Antonio Benfante; Simone Gerardin; Marta Bagatin (IOLTS, 2020)

Radiation Tolerant Multi-Bit Flip-Flop System With Embedded Timing Pre-Error Sensing. - Abhishek Jain 003; Andrea Mario Veggetti; Dennis Crippa; Antonio Benfante; Simone Gerardin; Marta Bagatin (IEEE J. Solid State Circuits, 2022)