Microkernel hypervisor for a hybrid ARM-FPGA platform. - Khoa Dang Pham; Abhishek Kumar Jain; Jin Cui; Suhaib A. Fahmy; Douglas L. Maskell (ASAP, 2013)

Virtualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform. - Abhishek Kumar Jain; Khoa Dang Pham; Jin Cui; Suhaib A. Fahmy; Douglas L. Maskell (J. Signal Process. Syst., 2014)

Efficient Overlay Architecture Based on DSP Blocks. - Abhishek Kumar Jain; Suhaib A. Fahmy; Douglas L. Maskell (FCCM, 2015)

Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq. - Abhishek Kumar Jain; Xiangwei Li; Suhaib A. Fahmy; Douglas L. Maskell (SIGARCH Comput. Archit. News, 2015)

Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs? - Abhishek Kumar Jain; Douglas L. Maskell; Suhaib A. Fahmy (DASC/PiCom/DataCom/CyberSciTech, 2016)

Throughput oriented FPGA overlays using DSP blocks. - Abhishek Kumar Jain; Douglas L. Maskell; Suhaib A. Fahmy (DATE, 2016)

DeCO: A DSP Block Based FPGA Accelerator Overlay with Low Overhead Interconnect. - Abhishek Kumar Jain; Xiangwei Li; Pranjul Singhai; Douglas L. Maskell; Suhaib A. Fahmy (FCCM, 2016)

An Area-Efficient FPGA Overlay using DSP Block based Time-multiplexed Functional Units. - Xiangwei Li; Abhishek Kumar Jain; Douglas L. Maskell; Suhaib A. Fahmy (CoRR, 2016)

Resource-Aware Just-in-Time OpenCL Compiler for Coarse-Grained FPGA Overlays. - Abhishek Kumar Jain; Douglas L. Maskell; Suhaib A. Fahmy (CoRR, 2017)

Architecture centric coarse-grained FPGA overlays - Abhishek Kumar Jain (2017)

A time-multiplexed FPGA overlay with linear interconnect. - Xiangwei Li; Abhishek Kumar Jain; Douglas L. Maskell; Suhaib A. Fahmy (DATE, 2018)

Microscope on Memory: MPSoC-Enabled Computer Memory System Assessments. - Abhishek Kumar Jain; G. Scott Lloyd; Maya B. Gokhale (FCCM, 2018)

Performance Assessment of Emerging Memories Through FPGA Emulation. - Abhishek Kumar Jain; G. Scott Lloyd; Maya B. Gokhale (IEEE Micro, 2019)

A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAs. - Abhishek Kumar Jain; Hossein Omidian; Henri Fraisse; Mansimran Benipal; Lisa Liu; Dinesh Gaitonde (FPL, 2020)

High Throughput Accelerator Interface Framework for a Linear Time-Multiplexed FPGA Overlay. - Xiangwei Li; Kizheppatt Vipin; Douglas L. Maskell; Suhaib A. Fahmy; Abhishek Kumar Jain (ISCAS, 2020)

Role of on-chip networks in building domain-specific architectures (DSAs) for sparse computations (invited). - Abhishek Kumar Jain (SLIP, 2020)

Sparse Deep Neural Network Acceleration on HBM-Enabled FPGA Platform. - Abhishek Kumar Jain; Sharan Kumar; Aashish Tripathi; Dinesh Gaitonde (HPEC, 2021)

Coarse Grained FPGA Overlay for Rapid Just-In-Time Accelerator Compilation. - Abhishek Kumar Jain; Douglas L. Maskell; Suhaib A. Fahmy (IEEE Trans. Parallel Distributed Syst., 2022)

Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs. - Abhishek Kumar Jain; Chirag Ravishankar; Hossein Omidian; Sharan Kumar; Maithilee Kulkarni; Aashish Tripathi; Dinesh Gaitonde (FCCM, 2023)

Entropy Maximization in Sparse Matrix by Vector Multiplication (maxESpMV). - Paolo D'Alberto; Abhishek Kumar Jain; Ismail Bustany; Henri Fraisse; Mansimran Benipal (CoRR, 2023)