Towards a Cost Metric for Nearest Neighbor Constraints in Reversible Circuits. - Abhoy Kole; Kamalika Datta; Indranil Sengupta 001; Robert Wille (RC, 2015)

A Heuristic for Linear Nearest Neighbor Realization of Quantum Circuits by SWAP Gate Insertion Using N-Gate Lookahead. - Abhoy Kole; Kamalika Datta; Indranil Sengupta 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

Exact Synthesis of Ternary Reversible Functions Using Ternary Toffoli Gates. - Abhoy Kole; P. Mercy Nesa Rani; Kamalika Datta; Indranil Sengupta 001; Rolf Drechsler (ISMVL, 2017)

Test Pattern Generation Effort Evaluation of Reversible Circuits. - Abhoy Kole; Robert Wille; Kamalika Datta; Indranil Sengupta 001 (RC, 2017)

Design of Efficient Quantum Circuits Using Nearest Neighbor Constraint in 2D Architecture. - Leniency Marbaniang; Abhoy Kole; Kamalika Datta; Indranil Sengupta 001 (RC, 2017)

Improved Decomposition of Multiple-Control Ternary Toffoli Gates Using Muthukrishnan-Stroud Quantum Gates. - P. Mercy Nesa Rani; Abhoy Kole; Kamalika Datta; Indranil Sengupta 001 (RC, 2017)

Improved NCV Gate Realization of Arbitrary Size Toffoli Gates. - Abhoy Kole; Kamalika Datta (VLSID, 2017)

A New Heuristic for N-Dimensional Nearest Neighbor Realization of a Quantum Circuit. - Abhoy Kole; Kamalika Datta; Indranil Sengupta 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Improved Mapping of Quantum Circuits to IBM QX Architectures. - Abhoy Kole; Stefan Hillmich; Kamalika Datta; Robert Wille; Indranil Sengupta 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

SAT-based Exact Synthesis of Ternary Reversible Circuits using a Functionally Complete Gate Library. - Abhoy Kole; Kamalika Datta; Indranil Sengupta 001; Rolf Drechsler (DSD, 2022)

Mapping Quantum Circuits to 2-Dimensional Quantum Architectures. - Kamalika Datta; Abhoy Kole; Indranil Sengupta 001; Rolf Drechsler (GI-Jahrestagung, 2022)

Nearest Neighbor Mapping of Quantum Circuits to Two-Dimensional Hexagonal Qubit Architecture. - Kamalika Datta; Abhoy Kole; Indranil Sengupta 001; Rolf Drechsler (ISMVL, 2022)

Extending the Design Space of Dynamic Quantum Circuits for Toffoli based Network. - Abhoy Kole; Arighna Deb; Kamalika Datta; Rolf Drechsler (DATE, 2023)

Verification of In-Memory Logic Design using ReRAM Crossbars. - Kamalika Datta; Arighna Deb; Fatemeh Shirinzadeh; Abhoy Kole; Saeideh Shirinzadeh; Rolf Drechsler (NEWCAS, 2023)

Improved Cost-Metric for Nearest Neighbor Mapping of Quantum Circuits to 2-Dimensional Hexagonal Architecture. - Kamalika Datta; Abhoy Kole; Indranil Sengupta 001; Rolf Drechsler (RC, 2023)

Exploiting the Benefits of Clean Ancilla Based Toffoli Gate Decomposition Across Architectures. - Abhoy Kole; Kamalika Datta; Philipp Niemann 001; Indranil Sengupta 001; Rolf Drechsler (RC, 2023)

Impact of sneak paths on in-memory logic design in memristive crossbars. - Kamalika Datta; Arighna Deb; Abhoy Kole; Rolf Drechsler (it Inf. Technol., 2023)

Towards Formal Verification for MAC-based In-Memory Computing. - Fatemeh Shirinzadeh; Kamalika Datta; Saeideh Shirinzadeh; Abhoy Kole; Rolf Drechsler (ATS, 2024)

Dynamic Realization of Multiple Control Toffoli Gate. - Abhoy Kole; Arighna Deb; Kamalika Datta; Rolf Drechsler (DATE, 2024)

Complete and Efficient Verification for a RISC-V Processor Using Formal Verification. - Lennart Weingarten; Kamalika Datta; Abhoy Kole; Rolf Drechsler (DATE, 2024)

Exploring the Potential of Decision Diagrams for Efficient In-Memory Design Verification. - Khushboo Qayyum; Abhoy Kole; Kamalika Datta; Muhammad Hassan 002; Rolf Drechsler (ACM Great Lakes Symposium on VLSI, 2024)

Design Automation Challenges and Benefits of Dynamic Quantum Circuit in Present NISQ Era and Beyond: (Invited Paper). - Abhoy Kole; Kamalika Datta; Rolf Drechsler (ISVLSI, 2024)

Is Simulation the only Alternative for Effective Verification of Dynamic Quantum Circuits? - Liam Hurwitz; Kamalika Datta; Abhoy Kole; Rolf Drechsler (RC, 2024)

Exploring the Potential of Dynamic Quantum Circuit for Improving Device Scalability. - Abhoy Kole; Kamalika Datta; Rolf Drechsler (SOCC, 2024)

In-Memory SAT-Solver for Self-Verification of Programmable Memristive Architectures. - Fatemeh Shirinzadeh; Arighna Deb; Saeideh Shirinzadeh; Abhoy Kole; Kamalika Datta; Rolf Drechsler (VLSID, 2024)

Exploiting the Extended Neighborhood of Hexagonal Qubit Architecture for Mapping Quantum Circuits. - Abhoy Kole; Kamalika Datta; Indranil Sengupta 001; Rolf Drechsler (ACM J. Emerg. Technol. Comput. Syst., 2024)

Towards an Automated Debugging Approach for Fault Identification in Quantum Circuits. - Anton Maidl; Abhoy Kole; Kamalika Datta; Jannis Stoppe; Rolf Drechsler (DDECS, 2025)

Multi-Input MAGIC Synthesis and Verification for In-Memory Computing Design. - Saeideh Nabipour; Kamalika Datta; Lennart Weingarten; Abhoy Kole; Rolf Drechsler (ISMVL, 2025)

Unlocking the Benefits of Dynamic Quantum Circuits in Resource Constraint Architecture. - Abhoy Kole; Mohammed E. Djeridane; Arighna Deb; Kamalika Datta; Indranil Sengupta 001; Rolf Drechsler (ISVLSI, 2025)

qSAT: Design of an Efficient Quantum Satisfiability Solver for Hardware Equivalence Checking. - Abhoy Kole; Mohammed E. Djeridane; Lennart Weingarten; Kamalika Datta; Rolf Drechsler (ACM J. Emerg. Technol. Comput. Syst., 2025)