Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity. - Zihan Xu; Abinash Mohanty; Pai-Yu Chen; Deepak Kadetotad; Binbin Lin; Jieping Ye; Sarma B. K. Vrudhula; Shimeng Yu; Jae-sun Seo; Yu Cao 001 (BICA, 2014)

Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning. - Deepak Kadetotad; Zihan Xu; Abinash Mohanty; Pai-Yu Chen; Binbin Lin; Jieping Ye; Sarma B. K. Vrudhula; Shimeng Yu; Yu Cao 001; Jae-sun Seo (BioCAS, 2014)

Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip. - Pai-Yu Chen; Deepak Kadetotad; Zihan Xu; Abinash Mohanty; Binbin Lin; Jieping Ye; Sarma B. K. Vrudhula; Jae-sun Seo; Yu Cao 001; Shimeng Yu (DATE, 2015)

Duty cycle shift under static/dynamic aging in 28nm HK-MG technology. - Ketul B. Sutaria; Pengpeng Ren; Abinash Mohanty; Xixiang Feng; Runsheng Wang; Ru Huang 001; Yu Cao 001 (IRPS, 2015)

Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration. - Deepak Kadetotad; Zihan Xu; Abinash Mohanty; Pai-Yu Chen; Binbin Lin; Jieping Ye; Sarma B. K. Vrudhula; Shimeng Yu; Yu Cao 001; Jae-sun Seo (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks. - Naveen Suda; Vikas Chandra; Ganesh Dasika; Abinash Mohanty; Yufei Ma 002; Sarma B. K. Vrudhula; Jae-sun Seo; Yu Cao 001 (FPGA, 2016)

High-performance face detection with CPU-FPGA acceleration. - Abinash Mohanty; Naveen Suda; Minkyu Kim 001; Sarma B. K. Vrudhula; Jae-sun Seo; Yu Cao 001 (ISCAS, 2016)

A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS. - Minkyu Kim 001; Abinash Mohanty; Deepak Kadetotad; Naveen Suda; Luning Wei; Pooja Saseendran; Xiaofei He 001; Yu Cao 001; Jae-sun Seo (ASP-DAC, 2017)

RTN in Scaled Transistors for On-Chip Random Seed Generation. - Abinash Mohanty; Ketul B. Sutaria; Hiromitsu Awano; Takashi Sato 001; Yu Cao 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Towards a Wearable Cough Detector Based on Neural Networks. - Prad Kadambi; Abinash Mohanty; Hao Ren; Jaclyn Smith; Kevin McGuinnes; Kimberly Holt; Armin Furtwaengler; Roberto Slepetys; Zheng Yang; Jae-sun Seo; Junseok Chae; Yu Cao 001; et al. (ICASSP, 2018)

Algorithm and Hardware Design for Efficient Deep Learning Inference. - Abinash Mohanty (2018)

Towards Efficient Neural Networks On-a-chip: Joint Hardware-Algorithm Approaches. - Xiaocong Du; Gokul Krishnan; Abinash Mohanty; Zheng Li 020; Gouranga Charan; Yu Cao 001 (CoRR, 2019)

A Real-Time 17-Scale Object Detection Accelerator With Adaptive 2000-Stage Classification in 65 nm CMOS. - Minkyu Kim 001; Abinash Mohanty; Deepak Kadetotad; Luning Wei; Xiaofei He 001; Yu Cao 001; Jae-sun Seo (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression. - Anupreetham Anupreetham; Mohamed Ibrahim; Mathew Hall; Andrew Boutros; Ajay Kuzhively; Abinash Mohanty; Eriko Nurvitadhi; Vaughn Betz; Yu Cao 001; Jae-sun Seo (FPL, 2021)

High Throughput FPGA-Based Object Detection via Algorithm-Hardware Co-Design. - Anupreetham Anupreetham; Mohamed Ibrahim; Mathew Hall; Andrew Boutros; Ajay Kuzhively; Abinash Mohanty; Eriko Nurvitadhi; Vaughn Betz; Yu Cao 001; Jae-Sun Seo (ACM Trans. Reconfigurable Technol. Syst., 2024)