A single cached copy data coherence scheme for multiprocessor systems. - Abraham Mendelson; Dhiraj K. Pradhan; Adit D. Singh (SIGARCH Comput. Archit. News, 1989)

Modeling of Live Lines and True Sharing in Multi-Cache Memory Systems. - Abraham Mendelson; Dominique Thiébaut; Dhiraj K. Pradhan (ICPP (1), 1990)

Modeling Live and Dead Lines in Cache Memory Systems. - Abraham Mendelson; Dominique Thiébaut; Dhiraj K. Pradhan (IEEE Trans. Computers, 1993)