High level circuit synthesis with system level Statistical Static Timing Analysis under process variation. - Abu M. Baker; Ling Wang; Yingtao Jiang (MWSCAS, 2013)

On a parallel decimal multiplier based on hybrid 8421-5421 BCD recoding. - Ming Zhu; Abu M. Baker; Yingtao Jiang (MWSCAS, 2013)

Real-time VLSI architecture for palm rejection using Wronskian Determinant. - Abu M. Baker; Yingtao Jiang (MWSCAS, 2015)