Logic minimization algorithms for three-level AND-OR-EXOR representations. - Abusaleh M. Jabir (2001)

MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions. - Abusaleh M. Jabir; Dhiraj K. Pradhan (DATE, 2004)

MODD for CF: a representation for fast evaluation of multiple-output functions. - T. L. Rajaprabhu; Ashutosh Kumar Singh 001; Abusaleh M. Jabir; Dhiraj K. Pradhan (HLDVT, 2004)

GASIM: a fast Galois field based simulator for functional model. - Dhiraj K. Pradhan; Ashutosh Kumar Singh 001; T. L. Rajaprabhu; Abusaleh M. Jabir (HLDVT, 2005)

Easily Testable Implementation for Bit Parallel Multipliers in GF (2m). - Hafizur Rahaman 001; Jimson Mathew; Abusaleh M. Jabir; Dhiraj K. Pradhan (HLDVT, 2006)

An efficient technique for synthesis and optimization of polynomials in GF(2m). - Abusaleh M. Jabir; Dhiraj K. Pradhan; Jimson Mathew (ICCAD, 2006)

A Graph-Based Unified Technique for Computing and Representing Coefficients over Finite Fields. - Abusaleh M. Jabir; Dhiraj K. Pradhan (IEEE Trans. Computers, 2007)

A Technique for Representing Multiple Output Binary Functions with Applications to Verification and Simulation. - Abusaleh M. Jabir; Dhiraj K. Pradhan; T. L. Rajaprabhu; Ashutosh Kumar Singh 001 (IEEE Trans. Computers, 2007)

Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection. - Jimson Mathew; Abusaleh M. Jabir; Dhiraj K. Pradhan (IOLTS, 2008)

Fault tolerant bit parallel finite field multipliers using LDPC codes. - Jimson Mathew; Jawar Singh; Abusaleh M. Jabir; Mohammad Hosseinabady; Dhiraj K. Pradhan (ISCAS, 2008)

Single Error Correcting Finite Field Multipliers Over GF(2m). - Jimson Mathew; Costas Argyrides; Abusaleh M. Jabir; Hafizur Rahaman 001; Dhiraj K. Pradhan (VLSI Design, 2008)

A Galois Field Based Logic Synthesis Approach with Testability. - Jimson Mathew; Hafizur Rahaman 001; Ashutosh Kumar Singh 001; Abusaleh M. Jabir; Dhiraj K. Pradhan (VLSI Design, 2008)

Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m). - Hafizur Rahaman 001; Jimson Mathew; Dhiraj K. Pradhan; Abusaleh M. Jabir (IEEE Trans. Computers, 2008)

GfXpress: A Technique for Synthesis and Optimization of GF(2m) Polynomials. - Abusaleh M. Jabir; Dhiraj K. Pradhan; Jimson Mathew (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

C-testable bit parallel multipliers over GF(2m). - Hafizur Rahaman 001; Jimson Mathew; Dhiraj K. Pradhan; Abusaleh M. Jabir (ACM Trans. Design Autom. Electr. Syst., 2008)

C-testable S-box implementation for secure advanced encryption standard. - Hafizur Rahaman 001; Jimson Mathew; Abusaleh M. Jabir; Dhiraj K. Pradhan (IOLTS, 2009)

Single error correctable bit parallel multipliers over GF(2m). - Jimson Mathew; Abusaleh M. Jabir; Hafizur Rahaman 001; Dhiraj K. Pradhan (IET Comput. Digit. Tech., 2009)

On the design of different concurrent EDC schemes for S-Box and GF(p). - Jimson Mathew; Hafizur Rahaman 001; Abusaleh M. Jabir; Saraju P. Mohanty; Dhiraj K. Pradhan (ISQED, 2010)

On the synthesis of attack tolerant cryptographic hardware. - Jimson Mathew; Savita Banerjee; Hafizur Rahaman 001; Dhiraj K. Pradhan; Saraju P. Mohanty; Abusaleh M. Jabir (VLSI-SoC, 2010)

A Galois field-based logic synthesis with testability. - Jimson Mathew; Abusaleh M. Jabir; Ashutosh Kumar Singh 001; Hafizur Rahaman 001; Dhiraj K. Pradhan (IET Comput. Digit. Tech., 2010)

Simplified bit parallel systolic multipliers for special class of galois field (2m) with testability. - Hafizur Rahaman 001; Jimson Mathew; Abusaleh M. Jabir; Dhiraj K. Pradhan (IET Comput. Digit. Tech., 2010)

A dynamically error correctable bit parallel Montgomery multiplier over binary extension fields. - Mahesh Poolakkaparambil; Jimson Mathew; Abusaleh M. Jabir; Dhiraj K. Pradhan (ECCTD, 2011)

BCH code based multiple bit error correction in finite field multiplier circuits. - Mahesh Poolakkaparambil; Jimson Mathew; Abusaleh M. Jabir; Dhiraj K. Pradhan; Saraju P. Mohanty (ISQED, 2011)

Low complexity cross parity codes for multiple and random bit error correction. - Mahesh Poolakkaparambil; Jimson Mathew; Abusaleh M. Jabir; Saraju P. Mohanty (ISQED, 2012)

An Investigation of Concurrent Error Detection over Binary Galois Fields in CNTFET and QCA Technologies. - Mahesh Poolakkaparambil; Jimson Mathew; Abusaleh M. Jabir; Saraju P. Mohanty (ISVLSI, 2012)

VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases. - Hafizur Rahaman 001; Jimson Mathew; Abusaleh M. Jabir; Dhiraj K. Pradhan (VDAT, 2012)

Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity. - Jimson Mathew; Saraju P. Mohanty; Shibaji Banerjee; Dhiraj K. Pradhan; Abusaleh M. Jabir (Comput. Electr. Eng., 2013)

Write scheme for multiple Complementary Resistive Switch (CRS) cells. - Adedotun Adeyemo; Jimson Mathew; Abusaleh M. Jabir; Dhiraj K. Pradhan (PATMOS, 2014)

Exploring error-tolerant low-power multiple-output read scheme for memristor-based memory arrays. - Adedotun A. Adeyemo; Jimson Mathew; Abusaleh M. Jabir; Dhiraj K. Pradhan (DFTS, 2015)

A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2m). - Mahesh Poolakkaparambil; Jimson Mathew; Abusaleh M. Jabir; Dhiraj K. Pradhan (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Analytic models for crossbar read operation. - Adedotun Adeyemo; Xiaohan Yang; Anu Bala; Jimson Mathew; Abusaleh M. Jabir (IOLTS, 2016)

Analytic models for crossbar write operation. - Adedotun Adeyemo; Xiaohan Yang; Anu Bala; Abusaleh M. Jabir (ISED, 2016)

High level abstraction of memristor model for neural network simulation. - Anu Bala; Adedotun Adeyemo; Xiaohan Yang; Abusaleh M. Jabir (ISED, 2016)

Novel memristive logic architectures. - Xiaohan Yang; Adedotun Adeyemo; Anu Bala; Abusaleh M. Jabir (PATMOS, 2016)

Learning method for ex-situ training of memristor crossbar based multi-layer neural network. - Anu Bala; Adedotun Adeyemo; Xiaohan Yang; Abusaleh M. Jabir (ICUMT, 2017)

Reliable gas sensing with memristive array. - Adedotun Adeyemo; Abusaleh M. Jabir; Jimson Mathew; Eugenio Martinelli; Corrado Di Natale; Marco Ottavi (IOLTS, 2017)

Parasitic effects on memristive logic architecture. - Xiaohan Yang; Adedotun Adeyemo; Anu Bala; Abusaleh M. Jabir (PATMOS, 2017)

Minimising Impact of Wire Resistance in Low-Power Crossbar Array Write Scheme. - Adedotun Adeyemo; Abusaleh M. Jabir; Jimson Mathew (J. Low Power Electron., 2017)

A Memristive Activation Circuit for Deep Learning Neural Networks. - Anu Bala; Xiaohan Yang; Adedotun Adeyemo; Abusaleh M. Jabir (ISED, 2018)

Fault Modeling and Simulation of Memristor based Gas Sensors. - Saurabh Khandelwal; Anu Bala; Vishal Gupta 002; Marco Ottavi; Eugenio Martinelli; Abusaleh M. Jabir (IOLTS, 2019)

The Missing Applications Found: Robust Design Techniques and Novel Uses of Memristors. - Marco Ottavi; Vishal Gupta 002; Saurabh Khandelwal; Shahar Kvatinsky; Jimson Mathew; Eugenio Martinelli; Abusaleh M. Jabir (IOLTS, 2019)

Novel techniques for memristive multifunction logic design. - Xiaohan Yang; Adedotun Adeyemo; Anu Bala; Abusaleh M. Jabir (Integr., 2019)

Efficient and Low Overhead Memristive Activation Circuit for Deep Learning Neural Networks. - Anu Bala; Xiaohan Yang; Adedotun Adeyemo; Abusaleh M. Jabir (J. Low Power Electron., 2019)

Sensing with Memristive Complementary Resistive Switch: Modelling and Simulations. - Vishal Gupta 002; Danilo Pellegrini; Saurabh Khandelwal; Abusaleh M. Jabir; Shahar Kvatinsky; Eugenio Martinelli; Corrado Di Natale; Marco Ottavi (DFT, 2020)

A Modelling Attack Resistant Low Overhead Memristive Physical Unclonable Function. - Xiaohan Yang; Saurabh Khandelwal; Aiqi Jiang; Abusaleh M. Jabir (DFT, 2020)

Yield Estimation of a Memristive Sensor Array. - Vishal Gupta 002; Saurabh Khandelwal; Giulio Panunzi; Eugenio Martinelli; Said Hamdioui; Abusaleh M. Jabir; Marco Ottavi (IOLTS, 2020)

Reliability Assessment of Memristor based Gas Sensor Array. - Vishal Gupta 002; Giulio Panunzi; Saurabh Khandelwal; Eugenio Martinelli; Abusaleh M. Jabir; Marco Ottavi (DFT, 2021)

A Memristive Architecture for Process Variation Aware Gas Sensing and Logic Operations. - Saurabh Khandelwal; Marco Ottavi; Eugenio Martinelli; Abusaleh M. Jabir (IOLTS, 2021)

Yield Evaluation of Faulty Memristive Crossbar Array-based Neural Networks with Repairability. - Anu Bala; Saurabh Khandelwal; Abusaleh M. Jabir; Marco Ottavi (IOLTS, 2022)

A Novel Digitisation Method for Pulse Switchable Memristive Chemical Sensors. - Meenakshi Devi; Saurabh Khandelwal; Marek Vidis; Tomas Plecenik; Abusaleh M. Jabir (DFT, 2024)

An AI-Assisted Connection Weight Prediction for Regression Testing of Integrated Circuits. - Abishaan Ravikumar; Xiaohan Yang; Rajendra Prasad; RajaNataraj Sivaraj; Alexander Rast; Abusaleh M. Jabir (DFT, 2024)