A Control Unit for a DEC PDP-8 Computer and a Burroughs Disk. - Ad J. van de Goor; C. Gordon Bell (IEEE Trans. Computers, 1969)

Design and Behavior of TSS/8: a PDP-8 Based Time-Sharing System. - Ad J. van de Goor; C. Gordon Bell; Donald A. Witcraft (IEEE Trans. Computers, 1969)

Effects of technical developments on system security. - Ad J. van de Goor (Comput. Secur., 1984)

Adapting UNIX for a Multiprocessor Environment. - M. D. Janssens; J. K. Annot; Ad J. van de Goor (Commun. ACM, 1986)

Comments on Morris's Starvation-Free Solution to the Mutual Exclusion Problem. - J. K. Annot; M. D. Janssens; Ad J. van de Goor (Inf. Process. Lett., 1986)

Multiprocessing memory subsystem. - Ad J. van de Goor; A. C. van Wijngaarden (Microprocess. Microsystems, 1987)

Using the page mode of dynamic RAMs to obtain a pseudo cache. - T. A. Peelen; Ad J. van de Goor (Microprocess. Microsystems, 1987)

Amore Address Mapping with Overlapped Rotating Entries. - G. J. Dekker; Ad J. van de Goor (IEEE Micro, 1987)

UNIX I/O in a Multiprocessor System. - Ad J. van de Goor; A. Moolenaar (USENIX Winter, 1988)

Speech synthesis system with unlimited vocabulary for the Dutch language. - Ad J. van de Goor; G. J. Nanninga (Microprocess. Microprogramming, 1988)

Transputer network with flexible topology. - P. Knoppers; Ad J. van de Goor; O. M. Gunhildsbu; P. Stravers (Microprocess. Microprogramming, 1988)

Software transparent cache consistency scheme for a VMEbus-based system. - Reinder J. Bril; Ad J. van de Goor (Microprocess. Microsystems, 1988)

Test Pattern Generation for API Faults in RAM. - Petra De Jong; Ad J. van de Goor (IEEE Trans. Computers, 1988)

Computer architecture and design. - Ad J. van de Goor (Addison-Wesley, 1989)

DOAS: an object oriented architecture supporting secure languages. - Ad J. van de Goor; Henk Corporaal (MICRO, 1989)

Distributed system design using Ada as a tool for prototyping. - A. M. Levy; Adrianus J. van de Goor; Jan van Katwijk (Microprocessing and Microprogramming, 1989)

TLS: a system for building and controlling transputer networks. - M. A. van Peursem; P. Knoppers; Ad J. van de Goor (Microprocessing and Microprogramming, 1989)

An Overview of Deterministic Functional RAM Chip Testing. - Ad J. van de Goor; C. A. Verruijt (ACM Comput. Surv., 1990)

Special architecture for high-performance scan conversion. - P. B. Franken; Ad J. van de Goor (Microprocessing and Microprogramming, 1990)

Self test for the Intel 8085. - Ad J. van de Goor; O. Jansen (Microprocessing and Microprogramming, 1990)

The Delft test system. - P. P. Meiler; Ad J. van de Goor (Microprocessing and Microprogramming, 1990)

Logic Synthesis of 100-percent Testable Logic Networks. - Gert-Jan Tromp; Ad J. van de Goor (ICCD, 1991)

Truth Table Verification for one-Dimensional CMOS ILA's. - Vlad. Hert; Ad J. van de Goor (Fault-Tolerant Computing Systems, 1991)

Locating Bridging Faults in Memory Arrays. - Ad J. van de Goor; P. C. M. van der Arend; Gert-Jan Tromp (ITC, 1991)

A low-cost tester for boundary scan. - Ad J. van de Goor; J. A. M. van Tetering (Microprocess. Microsystems, 1991)

Functional Testing of Current Microprocessors (applied to the Intel i860TM). - Ad J. van de Goor; Th. J. W. Verhallen (ITC, 1992)

Test Pattern Generation with Restrictors. - M. H. Konijnenburg; J. Th. van der Linden; Ad J. van de Goor (ITC, 1993)

Using March Tests to Test SRAMs. - Ad J. van de Goor (IEEE Des. Test Comput., 1993)

Functional Tests for Ring-Address SRAM-type FIFOs. - Ad J. van de Goor; Yervant Zorian; Ivo Schanstra (EDAC-ETC-EUROASIC, 1994)

A 16x16-bit Static CMOS Wave-Pipelined Multiplier. - Fabian Klass; Michael J. Flynn; Ad J. van de Goor (ISCAS, 1994)

Generating March Tests Automatically. - Ad J. van de Goor; B. Smit (ITC, 1994)

Parallel Pattern Fast Fault Simulation for Three-State Circuits and Bidirectional I/O. - J. Th. van der Linden; M. H. Konijnenburg; Ad J. van de Goor (ITC, 1994)

An Effective BIST Scheme for Ring-Address Type FIFOs. - Yervant Zorian; Ad J. van de Goor; Ivo Schanstra (ITC, 1994)

Automating the verification of memory tests. - Ad J. van de Goor; B. Smit (VTS, 1994)

Fault models and tests for Ring Address Type FIFOs. - Ad J. van de Goor; Ivo Schanstra; Yervant Zorian (VTS, 1994)

Test generation and three-state elements, buses, and bidirectionals. - J. Th. van der Linden; M. H. Konijnenburg; Ad J. van de Goor (VTS, 1994)

Effective march algorithms for testing single-order addressed memories. - Ad J. van de Goor; Yervant Zorian (J. Electron. Test., 1994)

Fast multiplication in VLSI using wave pipelining techniques. - Fabian Klass; Michael J. Flynn; Ad J. van de Goor (J. VLSI Signal Process., 1994)

Functional test for shifting-type FIFOs. - Ad J. van de Goor; Ivo Schanstra; Yervant Zorian (ED&TC, 1995)

Pseudo-exhaustive word-oriented DRAM testing. - Mark G. Karpovsky; Ad J. van de Goor; V. N. Yarmolik (ED&TC, 1995)

Coping with Re-usability Using Sequential ATPG: A Practical Case Study. - Jos van Sas; Erik Huyskens; Hans Naert; Fred Schell; Ad J. van de Goor (ITC, 1995)

Compact test sets for industrial circuits. - M. H. Konijnenburg; J. Th. van der Linden; Ad J. van de Goor (VTS, 1995)

Realistic Linked Memory Cell Array Faults. - Ad J. van de Goor; Georgi Gaydadjiev (Asian Test Symposium, 1996)

Circuit Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and Restrictors. - J. Th. van der Linden; M. H. Konijnenburg; Ad J. van de Goor (Asian Test Symposium, 1996)

Towards a Uniform Notation for Memory Tests. - Ad J. van de Goor; Aad Offerman; Ivo Schanstra (ED&TC, 1996)

RAM Testing Algorithm for Detection Linked Coupling Faults. - V. G. Mikitjuk; V. N. Yarmolik; Ad J. van de Goor (ED&TC, 1996)

Accelerated Compact Test Set Generation for Three-State Circuits. - M. H. Konijnenburg; J. Th. van der Linden; Ad J. van de Goor (ITC, 1996)

March LR: a test for realistic linked faults. - Ad J. van de Goor; Georgi Gaydadjiev; V. G. Mikitjuk; Vyacheslav N. Yarmolik (VTS, 1996)

March LA: a test for linked memory faults. - Ad J. van de Goor; Georgi Gaydadjiev; Vyacheslav N. Yarmolik; V. G. Mikitjuk (ED&TC, 1997)

The Implementation of Pseudo-Random Memory Tests on Commercial Memory Testers. - Ad J. van de Goor; Mike Lin (ITC, 1997)

Sequential Test Generation with Advanced Illegal State Search. - M. H. Konijnenburg; J. Th. van der Linden; Ad J. van de Goor (ITC, 1997)

Disturb Neighborhood Pattern Sensitive Fault. - Ad J. van de Goor; Issam B. S. Tlili (VTS, 1997)

Answers to the Key Issues. - Ad J. van de Goor (Asian Test Symposium, 1998)

Consequences of Port Restriction on Testing Address Decoders in Two-Port Memories. - Said Hamdioui; Ad J. van de Goor (Asian Test Symposium, 1998)

Complete Search in Test Generation for Industrial Circuits with Improved Bus-Conflict Detection. - J. Th. van der Linden; M. H. Konijnenburg; Ad J. van de Goor (Asian Test Symposium, 1998)

March Tests for Word-Oriented Memories. - Ad J. van de Goor; Issam B. S. Tlili (DATE, 1998)

Consequences of port restrictions on testing two-port memories. - Said Hamdioui; Ad J. van de Goor (ITC, 1998)

Semiconductor manufacturing process monitoring using built-in self-test for embedded memories. - Ivo Schanstra; Dharmajaya Lukita; Ad J. van de Goor; Kees Veelenturf; Paul J. van Wijnen (ITC, 1998)

Fault Models and Tests for Two-Port Memories. - Ad J. van de Goor; Said Hamdioui (VTS, 1998)

Automatic fault localization at chip level. - R. D. L. Stout; Ad J. van de Goor; R. E. Wolff (Microprocess. Microsystems, 1998)

Defining SRAM Resistive Defects and Their Simulation Stimuli. - Ad J. van de Goor; J. E. Simonse (Asian Test Symposium, 1999)

March Tests for Word-Oriented Two-Port Memories. - Said Hamdioui; Ad J. van de Goor (Asian Test Symposium, 1999)

Fault (In)Dependent Cost Estimates and Conflict-Directed Backtracking to Guide Sequential Circuit Test Generation. - M. H. Konijnenburg; Hans van der Linden; Ad J. van de Goor (Asian Test Symposium, 1999)

Industrial Evaluation of DRAM Tests. - Ad J. van de Goor; J. de Neef (DATE, 1999)

Illegal State Space Identification for Sequential Circuit Test Generation. - M. H. Konijnenburg; J. Th. van der Linden; Ad J. van de Goor (DATE, 1999)

Industrial evaluation of stress combinations for march tests applied to SRAMs. - Ad J. van de Goor; Ivo Schanstra (ITC, 1999)

Port interference faults in two-port memories. - Said Hamdioui; Ad J. van de Goor (ITC, 1999)

Testability of the Philips 80C51 micro-controller. - M. H. Konijnenburg; J. Th. van der Linden; Ad J. van de Goor (ITC, 1999)

Designing a Memory Module Tester. - Daniel P. Van der Velde; Ad J. van de Goor (MTDT, 1999)

Impact of memory cell array bridges on the faulty behavior in embedded DRAMs. - Zaid Al-Ars; Ad J. van de Goor (Asian Test Symposium, 2000)

An experimental analysis of spot defects in SRAMs: realistic fault models and tests. - Said Hamdioui; Ad J. van de Goor (Asian Test Symposium, 2000)

Test point insertion for compact test sets. - M. J. Geuzebroek; J. Th. van der Linden; Ad J. van de Goor (ITC, 2000)

Industrial evaluation of DRAM SIMM tests. - Ad J. van de Goor; A. Paalvast (ITC, 2000)

March Tests for Realistic Faults in Two-Port Memories. - Said Hamdioui; Ad J. van de Goor; Mike Rodgers; David Eastwick (MTDT, 2000)

Functional Memory Faults: A Formal Notation and a Taxonomy. - Ad J. van de Goor; Zaid Al-Ars (VTS, 2000)

Testing Address Decoder Faults in Two-Port Memories: Fault Models, Tests, Consequences of Port Restrictions, and Test Strategy. - Said Hamdioui; Ad J. van de Goor (J. Electron. Test., 2000)

A Memory Specific Notation for Fault Modeling. - Zaid Al-Ars; Ad J. van de Goor; Jens Braun; Detlev Richter (Asian Test Symposium, 2001)

Simulation and Development of Short Transparent Tests for RAM. - Serge N. Demidenko; Ad J. van de Goor; S. Henderson; P. Knoppers (Asian Test Symposium, 2001)

Detecting Unique Faults in Multi-port SRAMs. - Said Hamdioui; Ad J. van de Goor; David Eastwick; Mike Rodgers (Asian Test Symposium, 2001)

Tests for Resistive and Capacitive Defects in Address Decoders. - Matthias Klaus; Ad J. van de Goor (Asian Test Symposium, 2001)

Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs. - Zaid Al-Ars; Ad J. van de Goor (DATE, 2001)

Simulation based analysis of temperature effect on the faulty behavior of embedded DRAMs. - Zaid Al-Ars; Ad J. van de Goor; Jens Braun; Detlev Richter (ITC, 2001)

Transient Faults in DRAMs: Concepts, Analysis and Impact on Tests. - Zaid Al-Ars; Ad J. van de Goor (MTDT, 2001)

Realistic Fault Models and Test Procedures for Multi-Port SRAMs. - Said Hamdioui; Ad J. van de Goor; David Eastwick; Mike Rodgers (MTDT, 2001)

DRAM Specific Approximation of the Faulty Behavior of Cell Defects. - Zaid Al-Ars; Ad J. van de Goor (Asian Test Symposium, 2002)

Modeling Techniques and Tests for Partial Faults in Memory Devices. - Zaid Al-Ars; Ad J. van de Goor (DATE, 2002)

Minimal Test for Coupling Faults in Word-Oriented Memories. - Ad J. van de Goor; Magdy S. Abadir; Alan Carlin (DATE, 2002)

Address and Data Scrambling: Causes and Impact on Memory Tests. - Ad J. van de Goor; Ivo Schanstra (DELTA, 2002)

Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume. - M. J. Geuzebroek; J. Th. van der Linden; Ad J. van de Goor (ITC, 2002)

March SS: A Test for All Static Simple RAM Faults. - Said Hamdioui; Ad J. van de Goor; Mike Rodgers (MTDT, 2002)

Approximating Infinite Dynamic Behavior for DRAM Cell Defects. - Zaid Al-Ars; Ad J. van de Goor (VTS, 2002)

Testing Static and Dynamic Faults in Random Access Memories. - Said Hamdioui; Zaid Al-Ars; Ad J. van de Goor (VTS, 2002)

Efficient Tests for Realistic Faults in Dual-Port SRAMs. - Said Hamdioui; Ad J. van de Goor (IEEE Trans. Computers, 2002)

Thorough testing of any multiport memory with linear tests. - Said Hamdioui; Ad J. van de Goor (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces. - Zaid Al-Ars; Ad J. van de Goor (Asian Test Symposium, 2003)

March SL: A Test For All Static Linked Memory Faults. - Said Hamdioui; Zaid Al-Ars; Ad J. van de Goor; Mike Rodgers (Asian Test Symposium, 2003)

Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation. - Zaid Al-Ars; Ad J. van de Goor; Jens Braun; Detlev Richter (DATE, 2003)

Consequences of RAM Bitline Twisting for Test Coverage. - Ivo Schanstra; Ad J. van de Goor (DATE, 2003)

TPI for improving PR fault coverage of Boolean and three-state circuits. - M. J. Geuzebroek; Ad J. van de Goor (ETW, 2003)

Importance of dynamic faults for new SRAM technologies. - Said Hamdioui; Rob Wadsworth; John Delos Reyes; Ad J. van de Goor (ETW, 2003)

Systematic Memory Test Generation for DRAM Defects Causing Two Floating Nodes. - Zaid Al-Ars; Ad J. van de Goor (MTDT, 2003)

A Fault Primitive Based Analysis of Linked Faults in RAMs. - Zaid Al-Ars; Said Hamdioui; Ad J. van de Goor (MTDT, 2003)

Detecting Intra-Word Faults in Word-Oriented Memories. - Said Hamdioui; Ad J. van de Goor; Mike Rodgers (VTS, 2003)

Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests. - Said Hamdioui; Zaid Al-Ars; Ad J. van de Goor; Mike Rodgers (J. Electron. Test., 2003)

Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs. - Zaid Al-Ars; Ad J. van de Goor (IEEE Trans. Computers, 2003)

A Systematic Method for Modifying March Tests for Bit-Oriented Memories into Tests for Word-Oriented Memories. - Ad J. van de Goor; Issam B. S. Tlili (IEEE Trans. Computers, 2003)

Test generation and optimization for DRAM cell defects using electrical simulation. - Zaid Al-Ars; Ad J. van de Goor (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Soft Faults and the Importance of Stresses in Memory Testing. - Zaid Al-Ars; Ad J. van de Goor (DATE, 2004)

Tests for address decoder delay faults in RAMs due to inter-gate opens. - Ad J. van de Goor; Said Hamdioui; Zaid Al-Ars (ETS, 2004)

Detecting Faults in the Peripheral Circuits and an Evaluation of SRAM Tests. - Ad J. van de Goor; Said Hamdioui; Rob Wadsworth (ITC, 2004)

Influence of Bit Line Twisting on the Faulty Behavior of DRAMs. - Zaid Al-Ars; Martin Herzog; Ivo Schanstra; Ad J. van de Goor (MTDT, 2004)

The Effectiveness of the Scan Test and Its New Variants. - Ad J. van de Goor; Said Hamdioui; Zaid Al-Ars (MTDT, 2004)

The State-of-Art and Future Trends in Testing Embedded Memories. - Said Hamdioui; Georgi Gaydadjiev; Ad J. van de Goor (MTDT, 2004)

Effects of Bit Line Coupling on the Faulty Behavior of DRAMs. - Zaid Al-Ars; Said Hamdioui; Ad J. van de Goor (VTS, 2004)

An Industrial Evaluation of DRAM Tests. - Ad J. van de Goor (IEEE Des. Test Comput., 2004)

Memory Fault Modeling Trends: A Case Study. - Said Hamdioui; Rob Wadsworth; John Delos Reyes; Ad J. van de Goor (J. Electron. Test., 2004)

Linked faults in random access memories: concept, fault models, test algorithms, and industrial results. - Said Hamdioui; Zaid Al-Ars; Ad J. van de Goor; Mike Rodgers (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Framework for Fault Analysis and Test Generation in DRAMs. - Zaid Al-Ars; Said Hamdioui; Georg Mueller; Ad J. van de Goor (DATE, 2005)

Impact of stresses on the fault coverage of memory tests. - Said Hamdioui; Zaid Al-Ars; Ad J. van de Goor; Rob Wadsworth (MTDT, 2005)

Space of DRAM fault models and corresponding testing. - Zaid Al-Ars; Said Hamdioui; Ad J. van de Goor (DATE, 2006)

DRAM-Specific Space of Memory Tests. - Zaid Al-Ars; Said Hamdioui; Ad J. van de Goor; Georgi Gaydadjiev; Jörg E. Vollrath (ITC, 2006)

Opens and Delay Faults in CMOS RAM Address Decoders. - Said Hamdioui; Zaid Al-Ars; Ad J. van de Goor (IEEE Trans. Computers, 2006)

Influence of Bit-Line Coupling and Twisting on the Faulty Behavior of DRAMs. - Zaid Al-Ars; Said Hamdioui; Ad J. van de Goor; Sultan M. Al-Harbi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs. - Zaid Al-Ars; Said Hamdioui; Ad J. van de Goor; Georg Mueller (ITC, 2008)

New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults. - Ad J. van de Goor; Said Hamdioui; Georgi Nedeltchev Gaydadjiev; Zaid Al-Ars (Asian Test Symposium, 2009)

Memory testing with a RISC microcontroller. - Ad J. van de Goor; Georgi Gaydadjiev; Said Hamdioui (DATE, 2010)

Using a CISC microcontroller to test embedded memories. - Ad J. van de Goor; Said Hamdioui; Georgi Gaydadjiev (DDECS, 2010)

Low-cost, customized and flexible SRAM MBIST engine. - Ad J. van de Goor; Christian Jung; Said Hamdioui; Georgi Gaydadjiev (DDECS, 2010)

Advanced embedded memory testing: Reducing the defect per million level at lower test cost. - Said Hamdioui; Ad J. van de Goor (DDECS, 2010)

MBIST architecture framework based on orthogonal constructs. - Ad J. van de Goor; Said Hamdioui (IDT, 2010)

Generic, orthogonal and low-cost March Element based memory BIST. - Ad J. van de Goor; Said Hamdioui; Halil Kukner (ITC, 2011)