A multi-layered XML schema and design tool for reusing and integrating FPGA IP. - Adam Arnesen; Nathan Rollins; Michael J. Wirthlin (FPL, 2009)

Increasing Design Productivity through Core Reuse, Meta-data Encapsulation, and Synthesis. - Adam Arnesen; Kevin Ellsworth; Derrick Gibelyou; Travis Haroldsen; Jared Havican; Marc Padilla; Brent E. Nelson; Michael Rice; Michael J. Wirthlin (FPL, 2010)

Rapid and high-level constraint-driven prototyping using lab VIEW FPGA. - Hojin Kee; Swapnil Mhaske; David Uliana; Adam Arnesen; Newton Petersen; Taylor L. Riché; Dustyn Blasig; Tai Ly (GlobalSIP, 2014)