Trusted verification test bench development for Phase-Locked Loop (PLL) hardware insertion. - Adam G. Kimura; Kai-Wei Liu; Siddharth Prabhu; Steven B. Bibyk; Greg Creech (MWSCAS, 2013)

Quantifying metrics for analyzing integrated circuit design integrity. - Adam G. Kimura; Steven B. Bibyk (MWSCAS, 2016)

A Decomposition Workflow for Integrated Circuit Verification and Validation. - Adam G. Kimura; Jon Scholl; James Schaffranek; Matthew Sutter; Andrew Elliott; Mike Strizich; Glen David Via (J. Hardw. Syst. Secur., 2020)

Netlist Decompilation Workflow for Recovered Design Verification, Validation, and Assurance. - Katie Liszewski; Tim McDonley; Josh Delozier; Andrew Elliott; Dylan Jones; Matthew Sutter; Adam G. Kimura (IACR Cryptol. ePrint Arch., 2021)