An innovative sub-32nm SRAM voltage sense amplifier in double-gate CMOS insensitive to process variations and transistor mismatch. - Piotr Nasalski; Adam Makosiej; Bastien Giraud; Andrei Vladimirescu; Amara Amara (ICECS, 2008)

SRAM Voltage and Current Sense Amplifiers in sub-32nm Double-gate CMOS Insensitive to Process Variations and Transistor Mismatch. - Piotr Nasalski; Adam Makosiej; Bastien Giraud; Andrei Vladimirescu; Amara Amara (ISCAS, 2009)

Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization. - Adam Makosiej; Olivier Thomas; Andrei Vladimirescu; Amara Amara (DATE, 2012)

A 32nm tunnel FET SRAM for ultra low leakage. - Adam Makosiej; Rutwick Kumar Kashyap; Andrei Vladimirescu; Amara Amara; Costin Anghel (ISCAS, 2012)

CMOS SRAM scaling limits under optimum stability constraints. - Adam Makosiej; Olivier Thomas; Amara Amara; Andrei Vladimirescu (ISCAS, 2013)

Ultra-low leakage sub-32nm TFET/CMOS hybrid 32kb pseudo DualPort scratchpad with GHz speed for embedded applications. - Navneet Gupta; Adam Makosiej; Oliver Thomas; Amara Amara; Andrei Vladimirescu; Costin Anghel (ISCAS, 2015)

Sub-picowatt retention mode TFET memory for CMOS sensor processing nodes. - Andrei Vladimirescu; Costin Anghel; Amara Amara; Navneet Gupta; Adam Makosiej (IWASI, 2015)

3T-TFET bitcell based TFET-CMOS hybrid SRAM design for Ultra-Low Power applications. - Navneet Gupta; Adam Makosiej; Andrei Vladimirescu; Amara Amara; Costin Anghel (DATE, 2016)

16Kb hybrid TFET/CMOS reconfigurable CAM/SRAM array based on 9T-TFET bitcell. - Navneet Gupta; Adam Makosiej; Andrei Vladimirescu; Amara Amara; Costin Anghel (ESSDERC, 2016)

Ultra-compact SRAM design using TFETs for low power low voltage applications. - Navneet Gupta; Adam Makosiej; Andrei Vladimirescu; Amara Amara; Costin Anghel (ISCAS, 2016)

Ultra-Low-Power compact TFET Flip-Flop design for high-performance low-voltage applications. - Navneet Gupta; Adam Makosiej; Andrei Vladimirescu; Amara Amara; Costin Anghel (ISQED, 2016)

TFET NDR skewed inverter based sensing method. - Navneet Gupta; Adam Makosiej; Andrei Vladimirescu; Amara Amara; Sorin Cotofana; Costin Anghel (NANOARCH, 2016)

Tunnel FET based refresh-free-DRAM. - Navneet Gupta; Adam Makosiej; Andrei Vladimirescu; Amara Amara; Costin Anghel (DATE, 2017)

1.56GHz/0.9V energy-efficient reconfigurable CAM/SRAM using 6T-CMOS bitcell. - Navneet Gupta; Adam Makosiej; Andrei Vladimirescu; Amara Amara; Costin Anghel (ESSCIRC, 2017)

Tunnel FET based ultra-low-leakage compact 2T1C SRAM. - Navneet Gupta; Adam Makosiej; Andrei Vladimirescu; Amara Amara; Costin Anghel (ISQED, 2017)

Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology. - Reda Boumchedda; Jean-Philippe Noel; Bastien Giraud; Adam Makosiej; Marco Antonio Rios; Eduardo Esmanhotto; Emilien Bourde-Cicé; Mathis Bellet; David Turgis; Edith Beigné (NANOARCH, 2018)

Related references for extended TED submission (uDRAM and uSRAM reference papers). - Navneet Gupta; Adam Makosiej; Amara Amara; Andrei Vladimirescu; Costin Anghel (IEEE DataPort, 2018)

SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15, 000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency. - Ivan Miro Panades; Benoît Tain; Jean-Frédéric Christmann; David Coriat; Romain Lemaire; Clement Jany; Baudouin Martineau; Fabrice Chaix; Anthony Quelen; Emmanuel Pluchart; Jean-Philippe Noel; Reda Boumchedda; et al. (VLSI Circuits, 2020)

Energy Efficient Comparator-Less Current-Mode TFET-CMOS Co-Integrated Scalable Flash ADC. - Navneet Gupta; Hitesh Shrimali; Adam Makosiej; Andrei Vladimirescu; Amara Amara (MWSCAS, 2021)

SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration. - Ivan Miro-Panades; Benoît Tain; Jean-Frédéric Christmann; David Coriat; Romain Lemaire; Clement Jany; Baudouin Martineau; Fabrice Chaix; Guillaume Waltener; Emmanuel Pluchart; Jean-Philippe Noel; Adam Makosiej; et al. (IEEE J. Solid State Circuits, 2023)