A Novel Method of Two-Stage Decomposition Dedicated for PAL-based CPLDs. - Dariusz Kania; Józef Kulisz; Adam Milik (DSD, 2005)

Decomposition of Multi-Output Functions for CPLDs. - Dariusz Kania; Adam Milik; Józef Kulisz (DSD, 2005)

Common HDL-Matlab Simulation Environment. - Adam Milik; Andrzej Pulka (FDL, 2007)

VEST - An Intelligent Tool for Timing SoCs Verification Using UML Timing Diagrams. - Andrzej Pulka; Adam Milik (FDL, 2008)

Multithread RISC architecture based on programmable interleaved pipelining. - Andrzej Pulka; Adam Milik (ICECS, 2009)

The reconfigurable hardware accelerator for searching genome patterns. - Adam Milik; Andrzej Pulka (PDeS, 2009)

On efficient implementation of search algorithm for genome patterns. - Adam Milik; Andrzej Pulka (PDeS, 2010)

Logic synthesis based on decomposition for CPLDs. - Dariusz Kania; Adam Milik (Microprocess. Microsystems, 2010)

Automatic implementation of arithmetic operation in reconfigurable logic controllers. - Adam Milik; Andrzej Pulka (ECCTD, 2011)

On mapping of DSP48 units for arithmetic operation in reconfigurable logic controllers. - Adam Milik (PDeS, 2012)

Dynamic rescheduling of tasks in time predictable embedded systems. - Andrzej Pulka; Adam Milik (PDeS, 2012)

On Hardware Synthesis of Reconfigurable Logic Controllers from Ladder Diagrams According to IEC61131-3. - Adam Milik (PDeS, 2013)

On hardware synthesis and implementation of PLC programs in FPGAs. - Adam Milik (Microprocess. Microsystems, 2016)

Nonlinearity Measurement of a Voltage Ramp Using a Digital Technique. - Adam Milik; Edward Hrynkiewicz (J. Circuits Syst. Comput., 2017)

Multiple-Core PLC CPU Implementation and Programming. - Adam Milik (J. Circuits Syst. Comput., 2018)