Interactive online tutorial assistance for a first programming course. - Carol Hulls; Adam Neale; Ben Komalo; Val Petrov; David J. Brush (IEEE Trans. Educ., 2005)

Digitally programmable SRAM timing for nano-scale technologies. - Adam Neale; Manoj Sachdev (ISQED, 2011)

A 0.4 V 75 kbit SRAM macro in 28 nm CMOS featuring a 3-adjacent MBU correcting ECC. - Adam Neale; Manoj Sachdev (CICC, 2014)

Design and Analysis of an Adjacent Multi-bit Error Correcting Code for Nanoscale SRAMs. - Adam Neale (2014)

A low energy SRAM-based physically unclonable function primitive in 28 nm CMOS. - Adam Neale; Manoj Sachdev (CICC, 2015)

Adjacent-MBU-Tolerant SEC-DED-TAEC-yAED Codes for Embedded SRAMs. - Adam Neale; Maarten Jonkman; Manoj Sachdev (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

8T1R: A Novel Low-power High-speed RRAM-based Non-volatile SRAM Design. - Amr M. S. Tosson Abdelwahed; Adam Neale; Mohab H. Anis; Lan Wei (ACM Great Lakes Symposium on VLSI, 2016)

Hybrid Latch-Type Offset Tolerant Sense Amplifier for Low-Voltage SRAMs. - Dhruv Patel 002; Adam Neale; Derek Wright; Manoj Sachdev (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

On the Correlation of Laser-induced and High-Energy Proton Beam-induced Single Event Latchup. - Bahar Ajdari; Samwel Sekwao; Ricardo Ascázubi; Adam Neale; Norbert Seifert (IRPS, 2020)

A Reliability Overview of Intel's 10+ Logic Technology. - Rohit Grover; Tony Acosta; C. AnDyke; Emre Armagan; C. Auth; Sunny Chugh; K. Downes; M. Hattendorf; N. Jack; S. Joshi; R. Kasim; Gerald S. Leatherman; et al. (IRPS, 2020)

Body Biased Sense Amplifier With Auto-Offset Mitigation for Low-Voltage SRAMs. - Dhruv Patel 002; Adam Neale; Derek Wright; Manoj Sachdev (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)