Autonomous CMOS image sensor for real time target detection and tracking. - Adam Teman; Sagi Fisher; Liby Sudakov; Alexander Fish; Orly Yadid-Pecht (ISCAS, 2008)

Ultra-low Power Subthreshold Flip-flop Design. - Sagi Fisher; Adam Teman; Dmitry Vaysman; Alexander Gertsman; Orly Yadid-Pecht; Alexander Fish (ISCAS, 2009)

Low voltage SRAMs and the scalability of the 9T Supply Feedback SRAM. - Janna Mezhibovsky; Adam Teman; Alexander Fish (SoCC, 2011)

A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM). - Adam Teman; Lidor Pergament; Omer Cohen; Alexander Fish (IEEE J. Solid State Circuits, 2011)

A GIDL free tunneling gate driver for a low power non-volatile memory array. - Hadar Dagan; Adam Teman; Alexander Fish; Evgeny Pikhay; Vladislav Dayan; Yakov Roizin (ISCAS, 2012)

A low-cost low-power non-volatile memory for RFID applications. - Hadar Dagan; Adam Teman; Alexander Fish; Evgeny Pikhay; Vladislav Dayan; Yakov Roizin (ISCAS, 2012)

State space modeling for sub-threshold SRAM stability analysis. - Janna Mezhibovsky; Adam Teman; Alexander Fish (ISCAS, 2012)

Low-Voltage 96 dB Snapshot CMOS Image Sensor with 4.5 nW Power Dissipation per Pixel. - Arthur Spivak; Adam Teman; Alexander Belenky; Orly Yadid-Pecht; Alexander Fish (Sensors, 2012)

A 40-nm Sub-Threshold 5T SRAM Bit Cell With Improved Read and Write Stability. - Adam Teman; Anatoli Mordakhay; Janna Mezhibovsky; Alexander Fish (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A Low-Power DCVSL-Like GIDL-Free Voltage Driver for Low-Cost RFID Nonvolatile Memory. - Hadar Dagan; Adam Teman; Evgeny Pikhay; Vladislav Dayan; Anatoli Mordakhay; Yakov Roizin; Alexander Fish (IEEE J. Solid State Circuits, 2013)

Functionality and stability analysis of a 400 mV quasi-static RAM (QSRAM) bitcell. - Adam Teman; Anatoli Mordakhay; Alexander Fish (Microelectron. J., 2013)

4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes. - Robert Giterman; Adam Teman; Pascal Andreas Meinerzhagen; Andreas Burg 001; Alexander Fish (ISCAS, 2014)

A Low-Power Low-Cost 24 GHz RFID Tag With a C-Flash Based Embedded Memory. - Hadar Dagan; Aviv Shapira; Adam Teman; Anatoli Mordakhay; Samuel Jameson; Evgeny Pikhay; Vladislav Dayan; Yakov Roizin; Eran Socher; Alexander Fish (IEEE J. Solid State Circuits, 2014)

Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM. - Adam Teman; Pascal Andreas Meinerzhagen; Robert Giterman; Alexander Fish; Andreas Burg 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI. - Adam Teman; Davide Rossi; Pascal Andreas Meinerzhagen; Luca Benini; Andreas Peter Burg (ASP-DAC, 2015)

Mitigating the impact of faults in unreliable memories for error-resilient applications. - Shrikanth Ganapathy; Georgios Karakonstantis; Adam Teman; Andreas Burg 001 (DAC, 2015)

Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories. - Adam Teman; Georgios Karakonstantis; Robert Giterman; Pascal Andreas Meinerzhagen; Andreas Peter Burg (DATE, 2015)

An overlap-contention free true-single-phase clock dual-edge-triggered flip-flop. - Andrea Bonetti; Adam Teman; Andreas Burg 001 (ISCAS, 2015)

Approximate computing with unreliable dynamic memories. - Shrikanth Ganapathy; Adam Teman; Robert Giterman; Andreas Burg 001; Georgios Karakonstantis (NEWCAS, 2015)

A Fast Modular Method for True Variation-Aware Separatrix Tracing in Nanoscaled SRAMs. - Adam Teman; Roman Visotsky (IEEE Trans. Very Large Scale Integr. Syst., 2015)

193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. - Davide Rossi; Antonio Pullini; Igor Loi; Michael Gautschi; Frank Kagan Gürkaynak; Adam Teman; Jeremy Constantin; Andreas Burg 001; Ivan Miro Panades; Edith Beigné; Fabien Clermidy; Fady Abouzeid; et al. (COOL Chips, 2016)

DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment. - Jeremy Constantin; Andrea Bonetti; Adam Teman; Thomas Christoph Müller; Lorenz Schmid; Andreas Burg 001 (ESSCIRC, 2016)

A low-power correlator for wakeup receivers with algorithm pruning through early termination. - Reza Ghanaatian; Paul N. Whatmough; Jeremy Constantin; Adam Teman; Andreas Burg 001 (ISCAS, 2016)

A process compensated gain cell embedded-DRAM for ultra-low-power variation-aware design. - Robert Giterman; Adam Teman; Pascal Meinerzhagen; Alexander Fish; Andreas Burg 001 (ISCAS, 2016)

Synthesis of Dual Mode Logic. - Lior Moyal; Itamar Levi; Adam Teman; Alexander Fish (Integr., 2016)

Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs. - Noa Edri; Pascal Meinerzhagen; Adam Teman; Andreas Burg 001; Alexander Fish (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement. - Adam Teman; Davide Rossi; Pascal Meinerzhagen; Luca Benini; Andreas Burg 001 (ACM Trans. Design Autom. Electr. Syst., 2016)

A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications. - Lior Atias; Adam Teman; Robert Giterman; Pascal Meinerzhagen; Alexander Fish (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications. - Robert Giterman; Adam Teman; Pascal Andreas Meinerzhagen; Lior Atias; Andreas Burg 001; Alexander Fish (IEEE Trans. Very Large Scale Integr. Syst., 2016)

An 800 Mhz mixed-VT 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications. - Robert Giterman; Alexander Fish; Narkis Geuli; Elad Mentovich; Andreas Burg 001; Adam Teman (ESSCIRC, 2017)

A 594 Gbps LDPC Decoder Based on Finite-Alphabet Message Passing. - Reza Ghanaatian; Alexios Balatsoukas-Stimming; Thomas Christoph Müller; Michael Meidlinger; Gerald Matz; Adam Teman; Andreas Burg 001 (CoRR, 2017)

Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster. - Davide Rossi; Antonio Pullini; Igor Loi; Michael Gautschi; Frank Kagan Gürkaynak; Adam Teman; Jeremy Constantin; Andreas Burg 001; Ivan Miro Panades; Edith Beigné; Fabien Clermidy; Philippe Flatresse; et al. (IEEE Micro, 2017)

Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters. - Andrea Bonetti; Adam Teman; Philippe Flatresse; Andreas Burg 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Hybrid GC-eDRAM/SRAM Bitcell for Robust Low-Power Operation. - Robert Giterman; Adam Teman; Pascal Meinerzhagen (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes. - Andrea Bonetti; Nicholas Preyss; Adam Teman; Andreas Burg 001 (ACM Trans. Design Autom. Electr. Syst., 2017)

Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications. - Robert Giterman; Lior Atias; Adam Teman (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A 0.65-V, 500-MHz Integrated Dynamic and Static RAM for Error Tolerant Applications. - Amit Kazimirsky; Adam Teman; Noa Edri; Alexander Fish (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Configurable Multi-Port Dynamic Bitcell with Internal Refresh Mechanism. - Roman Golman; Robert Giterman; Adam Teman (ICECS, 2018)

High Density GC-eDRAM Design in 16nm FinFET. - Amir Shalom; Robert Giterman; Adam Teman (ICECS, 2018)

Live Demonstration: An 800 Mhz Gain-Cell Embedded DRAM in 28 nm CMOS Bulk Process for Approximate Computing Applications. - Robert Giterman; Roman Golman; Amir Shalom; Or Maltabashi; Alexander Fish; Adam Teman (ISCAS, 2018)

A 5-Transistor Ternary Gain-Cell eDRAM with Parallel Sensing. - Or Maltabashi; Hanan Marinberg; Robert Giterman; Adam Teman (ISCAS, 2018)

An 800-MHz Mixed- VT 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications. - Robert Giterman; Alexander Fish; Narkis Geuli; Elad Mentovich; Andreas Burg 001; Adam Teman (IEEE J. Solid State Circuits, 2018)

A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI. - Robert Giterman; Alexander Fish; Andreas Burg 001; Adam Teman (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Gain-Cell Embedded DRAM-Based Physical Unclonable Function. - Robert Giterman; Yoav Weizman; Adam Teman (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing. - Reza Ghanaatian; Alexios Balatsoukas-Stimming; Thomas Christoph Müller; Michael Meidlinger; Gerald Matz; Adam Teman; Andreas Burg 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

TEMPO: Thermal-Efficient Management of Power in High-Throughput Network Switches. - Tom Munk; Hillel Kugler; Ofir Maori; Adam Teman (VLSI-DAT, 2019)

Improving Energy-Efficiency in Dynamic Memories Through Retention Failure Detection. - Robert Giterman; Roman Golman; Adam Teman (IEEE Access, 2019)

GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI. - Robert Giterman; Andrea Bonetti; Andreas Burg 001; Adam Teman (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

WavePro: Clock-less Wave-Propagated Pipeline Compiler for Low-Power and High-Throughput Computation. - Yehuda Kra; Tzachi Noy; Adam Teman (DATE, 2020)

GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI. - Robert Giterman; Andrea Bonetti; Andreas Burg 001; Adam Teman (ISCAS, 2020)

Improved Read Access in GC-eDRAM Memory by Dual-Negative Word-Line Technique. - Roman Golman; Robert Giterman; Odem Harel; Adam Teman (ISCAS, 2020)

Physically Aware Affinity-Driven Multiplier Implementation. - Or Maltabashi; Yehuda Kra; Adam Teman (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space. - Robert Giterman; Andrea Bonetti; Ester Vicario Bravo; Tzachi Noy; Adam Teman; Andreas Burg 001 (IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020)

Design of a Refresh-Controller for GC-eDRAM Based FIFOs. - Tzachi Noy; Adam Teman (IEEE Trans. Circuits Syst., 2020)

Gain-Cell Embedded DRAMs: Modeling and Design Space. - Andrea Bonetti; Roman Golman; Robert Giterman; Adam Teman; Andreas Burg 001 (IEEE Trans. Very Large Scale Integr. Syst., 2020)

WP 2.0: Signoff-Quality Implementation and Validation of Energy-Efficient Clock-Less Wave Propagated Pipelining. - Yehuda Kra; Tzachi Noy; Adam Teman (DATE, 2021)

4T Gain-Cell Providing Unlimited Availability through Hidden Refresh with 1W1R Functionality. - Einat Levy; Aharon Sfez; Roman Golman; Odem Harel; Adam Teman (ISCAS, 2021)

Refresh Algorithm for Ensuring 100% Memory Availability in Gain-Cell Embedded DRAM Macros. - Roman Golman; Netanel Nachum; Tomer Cohen; Robert Giterman; Adam Teman (IEEE Access, 2021)

Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for Approximate Matching Applications. - Esteban Garzón; Roman Golman; Zuher Jahshan; Robert Hanhan; Natan Vinshtok-Melnik; Marco Lanuzza; Adam Teman; Leonid Yavits (CoRR, 2021)

Gain-Cell Embedded DRAM Under Cryogenic Operation - A First Study. - Esteban Garzón; Yosi Greenblatt; Odem Harel; Marco Lanuzza; Adam Teman (IEEE Trans. Very Large Scale Integr. Syst., 2021)

SerOpt: Transistor Sizing Algorithm and Optimization Utility for Minimizing Soft Error Rate. - Yehuda Kra; Yoav Weizman; Adam Teman (DCIS, 2022)

EDAM: edit distance tolerant approximate matching content addressable memory. - Robert Hanhan; Esteban Garzón; Zuher Jahshan; Adam Teman; Marco Lanuzza; Leonid Yavits (ISCA, 2022)

A RISC-V-based Research Platform for Rapid Design Cycle. - Esteban Garzón; Roman Golman; Odem Harel; Tzachi Noy; Yehuda Kra; Asaf Pollock; Slava Yuzhaninov; Yonatan Shoshan; Yehuda Rudin; Yoav Weizman; Marco Lanuzza; Adam Teman (ISCAS, 2022)

Silicon-Proven Clockless Wave-Propagated Pipelining for High-Throughput, Energy-Efficient Processing. - Yehuda Kra; Adam Teman (ISCAS, 2022)

Evaluation of Dual Mode Logic Under Cryogenic Temperatures. - Inbal Stanger; Noam Roknian; Yonatan Shoshan; Zafrir Levy; Yoav Weizman; Edoardo Charbon; Adam Teman; Alexander Fish (ISCAS, 2022)

Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for DNA Classification. - Esteban Garzón; Roman Golman; Zuher Jahshan; Robert Hanhan; Natan Vinshtok-Melnik; Marco Lanuzza; Adam Teman; Leonid Yavits (IEEE Access, 2022)

Adjusting Thermal Stability in Double-Barrier MTJ for Energy Improvement in Cryogenic STT-MRAMs. - Esteban Garzón; Raffaele De Rose; Felice Crupi; Lionel Trojman; Adam Teman; Marco Lanuzza (CoRR, 2022)

AIDA: Associative In-Memory Deep Learning Accelerator. - Esteban Garzón; Adam Teman; Marco Lanuzza; Leonid Yavits (IEEE Micro, 2022)

STT-MRAM Technology For Energy-Efficient Cryogenic Memory Applications. - Esteban Garzón; Leonid Yavits; Adam Teman; Marco Lanuzza (LASCAS, 2023)

Overview of Cryogenic Operation in Nanoscale Technology Nodes. - Noam Roknian; Yonatan Shoshan; Inbal Stanger; Adam Teman; Edoardo Charbon; Alexander Fish (LASCAS, 2023)

A Low-Energy DMTJ-Based Ternary Content- Addressable Memory With Reliable Sub-Nanosecond Search Operation. - Esteban Garzón; Leonid Yavits; Giovanni Finocchio; Mario Carpentieri; Adam Teman; Marco Lanuzza (IEEE Access, 2023)

Efficient Implementation of Many-Ported Memories by Using Standard-Cell Memory Approach. - Hanan Marinberg; Esteban Garzón; Tzachi Noy; Marco Lanuzza; Adam Teman (IEEE Access, 2023)

AM4: MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing. - Esteban Garzón; Marco Lanuzza; Adam Teman; Leonid Yavits (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

A Low-Complexity Sensing Scheme for Approximate Matching Content-Addressable Memory. - Esteban Garzón; Roman Golman; Marco Lanuzza; Adam Teman; Leonid Yavits (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Selfie5: An Autonomous, Self-Contained Verification Approach for High-Throughput Random Testing of Programmable Processors. - Yehuda Kra; Naama Kra; Adam Teman (DATE, 2024)

A 4T GC-eDRAM Bitcell with Differential Readout Mechanism For High Performance Applications. - Roman Golman; Avinoam Segev; Adam Teman (PRIME, 2024)

Basecalling by Statistical Profiling and Hardware-Accelerated Convolutional Neural Network. - Yehuda Kra; Yehuda Rudin; Alexander Fish; Adam Teman (PRIME, 2024)

Methodologies for Device Characterization in Cryogenic Temperatures. - Noam Roknian; Yonatan Shoshan; Inbal Stanger; Menachem Goldzweig; Yoav Weizmann; Adam Teman; Edoardo Charbon; Alexander Fish (PRIME, 2024)

FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture. - Esteban Garzón; Robert Hanhan; Marco Lanuzza; Adam Teman; Leonid Yavits (IEEE Access, 2024)

HAMSA-DI: A Low-Power Dual-Issue RISC-V Core Targeting Energy-Efficient Embedded Systems. - Yehuda Kra; Yonatan Shoshan; Yehuda Rudin; Adam Teman (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Revisiting Dynamic Logic - A True Candidate for Energy-Efficient Cryogenic Operation in Nanoscaled Technologies. - Inbal Stanger; Noam Roknian; Netanel Shavit; Yonatan Shoshan; Yoav Weizman; Adam Teman; Edoardo Charbon; Alexander Fish (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Designing Precharge-Free Energy-Efficient Content-Addressable Memories. - Ramiro Taco; Esteban Garzón; Robert Hanhan; Adam Teman; Leonid Yavits; Marco Lanuzza (IEEE Trans. Very Large Scale Integr. Syst., 2024)

LPRE: Logarithmic Posit-enabled Reconfigurable edge-AI Engine. - Omkar Kokane; Mukul Lokhande; Gopal Raut; Adam Teman; Santosh Kumar Vishvakarma (ISCAS, 2025)

Towards Low-Power High-Performance Content-Addressable Memory: A Robust Precharge-Free Approach. - Ramiro Taco; Esteban Garzón; Adam Teman; Leonid Yavits; Marco Lanuzza (ISCAS, 2025)

Retrospective: A CORDIC Based Configurable Activation Function for NN Applications. - Omkar Kokane; Gopal Raut; Salim Ullah; Mukul Lokhande; Adam Teman; Akash Kumar 001; Santosh Kumar Vishvakarma (ISVLSI, 2025)

CORDIC Is All You Need. - Omkar Kokane; Adam Teman; Anushka Jha; Guru Prasath SL; Gopal Raut; Mukul Lokhande; S. V. Jaya Chand; Tanushree Dewangan; Santosh Kumar Vishvakarma (CoRR, 2025)

A 16-kB 65-nm GC-eDRAM Macro With Internal Bias Voltage Generation Providing Over 100-μs Retention Time. - Odem Harel; Halil Andaç Yigit; Eliana Feifel; Robert Giterman; Andreas Burg 001; Adam Teman (IEEE J. Solid State Circuits, 2025)

A 128-kbit Approximate Search-Capable Content-Addressable Memory (CAM) With Tunable Hamming Distance. - Esteban Garzón; Eyal Rechef; Roman Golman; Odem Harel; Yuval Harary; Paz Snapir; Marco Lanuzza; Adam Teman; Leonid Yavits (IEEE J. Solid State Circuits, 2025)