A SystemC TLM2 model of communication in wormhole switched Networks-On-Chip. - Adán Kohler; Martin Radetzki (FDL, 2009)

Modellierung und Simulation von Networks-on-Chip mit OSCI TLM2. - Adán Kohler; Martin Radetzki (MBMV, 2009)

Fault-tolerant architecture and deflection routing for degradable NoC switches. - Adán Kohler; Martin Radetzki (NOCS, 2009)

An intelligent deflection router for networks-on-chip. - Martin Radetzki; Adán Kohler (WISES, 2009)

Degradability Enabled Routing for Network-on-Chip Switches (Routingverfahren zur Unterstützung der Degradierbarkeit von Network-on-Chip Switches). - Gert Schley; Martin Radetzki; Adán Kohler (it Inf. Technol., 2010)

Fault Tolerant Network on Chip Switching With Graceful Performance Degradation. - Adán Kohler; Gert Schley; Martin Radetzki (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Cost-Based Deflection Routing for Intelligent NoC Switches. - Martin Radetzki; Adán Kohler (Solutions on Embedded Systems, 2011)

Low-Latency Collectives for the Intel SCC. - Adán Kohler; Martin Radetzki; Philipp Gschwandtner; Thomas Fahringer (CLUSTER, 2012)

Minimal MPI as programming interface for multicore System-on-Chips. - Adán Kohler; Juan Manuel Castillo-Sanchez; Joachim Gross; Martin Radetzki (FDL, 2012)

Optimized Reduce for Mesh-Based NoC Multiprocessors. - Adán Kohler; Martin Radetzki (IPDPS Workshops, 2012)

Latency-optimized Collectives for High Performance on Intel's Single-chip Cloud Computer. - Adán Kohler; Martin Radetzki (MARC@RWTH, 2012)

Power Management for High-Performance Applications on Network-on-Chip-Based Multiprocessors. - Adán Kohler; Martin Radetzki (GreenCom/iThings/CPScom, 2013)