HAShCache: Heterogeneity-Aware Shared DRAMCache for Integrated Heterogeneous Systems. - Adarsh Patil 002; Ramaswamy Govindarajan (ACM Trans. Archit. Code Optim., 2017)

TLB and Pagewalk Performance in Multicore Architectures with Large Die-Stacked DRAM Cache. - Adarsh Patil 002 (CoRR, 2020)

Dvé: Improving DRAM Reliability and Performance On-Demand via Coherent Replication. - Adarsh Patil 002; Vijay Nagarajan; Rajeev Balasubramonian; Nicolai Oswald (ISCA, 2021)

Āpta: Fault-tolerant object-granular CXL disaggregated memory for accelerating FaaS. - Adarsh Patil 002; Vijay Nagarajan; Nikos Nikoleris; Nicolai Oswald (DSN, 2023)

UDON: A case for offloading to general purpose compute on CXL memory. - Jon Hermes; Josh Minor; Minjun Wu; Adarsh Patil 002; Eric Van Hensbergen (CoRR, 2024)

Improving compiler support for SIMD offload using Arm Streaming SVE. - Mohamed Husain Noor Mohamed; Adarsh Patil 002; Latchesar Ionkov; Eric Van Hensbergen (CoRR, 2025)