A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS. - Jafar Savoj; Kenny C.-H. Hsieh; Parag Upadhyaya; Fu-Tai An; Ade Bekele; Stanley Chen; Xuewen Jiang; Kang Wei Lai; Chi Fung Poon; Aman Sewani; Didem Turker; Karthik Venna; et al. (VLSIC, 2012)

3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS. - Parag Upadhyaya; Jafar Savoj; Fu-Tai An; Ade Bekele; Anup P. Jose; Bruce Xu; Zhaoyin Daniel Wu; Didem Turker; Hesam Amir Aslanzadeh; Hiva Hedayati; Jay Im; Siok-Wei Lim; et al. (ISSCC, 2015)

A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS. - Yohan Frans; Declan Carey; Marc Erett; Hesam Amir Aslanzadeh; Wayne Y. Fang; Didem Turker; Anup P. Jose; Adebabay Bekele; Jay Im; Parag Upadhyaya; Zhaoyin Daniel Wu; Kenny C.-H. Hsieh; et al. (IEEE J. Solid State Circuits, 2015)

A fully-adaptive wideband 0.5-32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technology. - Parag Upadhyaya; Ade Bekele; Didem Turker Melek; Haibing Zhao; Jay Im; Junho Cho; Kee Hian Tan; Scott McLeod; Stanley Chen; Wenfeng Zhang; Yohan Frans; Ken Chang (VLSI Circuits, 2016)

A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs. - Didem Turker; Ade Bekele; Parag Upadhyaya; Bob Verbruggen; Ying Cao 010; Shaojun Ma; Christophe Erdmann; Brendan Farley; Yohan Frans; Ken Chang (ISSCC, 2018)

A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET. - Jay Im; Stanley Chen; Dave Freitas; Adam Chou; Lei Zhou; Ian Zhuang; Tim Cronin; David Mahashin; Winson Lin; Kok Lim Chan; Hongyuan Zhao; Kee Hian Tan; et al. (VLSI Circuits, 2018)

6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET. - Jay Im; Kevin Zheng; Adam Chou; Lei Zhou; Jae Wook Kim; Stanley Chen; Yipeng Wang 003; Hao-Wei Hung; Kee Hian Tan; Winson Lin; Arianne Roldan; Declan Carey; et al. (ISSCC, 2020)

A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET. - Jay Im; Kevin Zheng; Chuen-Huei Adam Chou; Lei Zhou; Jae Wook Kim; Stanley Chen; Yipeng Wang 003; Hao-Wei Hung; Kee Hian Tan; Winson Lin; Arianne Roldan; Declan Carey; et al. (IEEE J. Solid State Circuits, 2021)

A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies. - Mayank Raj; Chuan Xie; Ade Bekele; Adam Chou; Wenfeng Zhang; Ying Cao 010; Jae Wook Kim; Nakul Narang; Hongyuan Zhao; Yipeng Wang 003; Kee Hian Tan; Winson Lin; et al. (ISSCC, 2023)

Adaptive Wavelength Tracking and Temperature Tuning of A 45Gbps Coupled Ring Resonator Based DWDM Link. - Zhaowen Wang; Ade Bekele; Mingshan Li; Mayank Raj; Chuan Xie; Anish Joshi; Gareeyasee Saha; Zakriya Mohammed; Stuart Daudlin; Parag Upadhyaya; Yohan Frans (OFC, 2025)