Write scheme for multiple Complementary Resistive Switch (CRS) cells. - Adedotun Adeyemo; Jimson Mathew; Abusaleh M. Jabir; Dhiraj K. Pradhan (PATMOS, 2014)

Exploring error-tolerant low-power multiple-output read scheme for memristor-based memory arrays. - Adedotun A. Adeyemo; Jimson Mathew; Abusaleh M. Jabir; Dhiraj K. Pradhan (DFTS, 2015)

Analytic models for crossbar read operation. - Adedotun Adeyemo; Xiaohan Yang; Anu Bala; Jimson Mathew; Abusaleh M. Jabir (IOLTS, 2016)

Analytic models for crossbar write operation. - Adedotun Adeyemo; Xiaohan Yang; Anu Bala; Abusaleh M. Jabir (ISED, 2016)

High level abstraction of memristor model for neural network simulation. - Anu Bala; Adedotun Adeyemo; Xiaohan Yang; Abusaleh M. Jabir (ISED, 2016)

Novel memristive logic architectures. - Xiaohan Yang; Adedotun Adeyemo; Anu Bala; Abusaleh M. Jabir (PATMOS, 2016)

Learning method for ex-situ training of memristor crossbar based multi-layer neural network. - Anu Bala; Adedotun Adeyemo; Xiaohan Yang; Abusaleh M. Jabir (ICUMT, 2017)

Reliable gas sensing with memristive array. - Adedotun Adeyemo; Abusaleh M. Jabir; Jimson Mathew; Eugenio Martinelli; Corrado Di Natale; Marco Ottavi (IOLTS, 2017)

Parasitic effects on memristive logic architecture. - Xiaohan Yang; Adedotun Adeyemo; Anu Bala; Abusaleh M. Jabir (PATMOS, 2017)

Minimising Impact of Wire Resistance in Low-Power Crossbar Array Write Scheme. - Adedotun Adeyemo; Abusaleh M. Jabir; Jimson Mathew (J. Low Power Electron., 2017)

A Memristive Activation Circuit for Deep Learning Neural Networks. - Anu Bala; Xiaohan Yang; Adedotun Adeyemo; Abusaleh M. Jabir (ISED, 2018)

Novel techniques for memristive multifunction logic design. - Xiaohan Yang; Adedotun Adeyemo; Anu Bala; Abusaleh M. Jabir (Integr., 2019)

Efficient and Low Overhead Memristive Activation Circuit for Deep Learning Neural Networks. - Anu Bala; Xiaohan Yang; Adedotun Adeyemo; Abusaleh M. Jabir (J. Low Power Electron., 2019)